ELECTRONIC ASSEMBLY
    1.
    发明公开
    ELECTRONIC ASSEMBLY 审中-公开

    公开(公告)号:US20240136308A1

    公开(公告)日:2024-04-25

    申请号:US18401703

    申请日:2024-01-01

    CPC classification number: H01L23/642 H01L23/49822 H01L23/49838 H01L28/60

    Abstract: An embodiment of the disclosure provides an electronic assembly including a stacked structure, a first integrated circuit, a first passive component, and a first electrode. The stacked structure comprises a plurality of insulating layers and a plurality of conductive layers. The first passive component is disposed between the stacked structure and the first integrated circuit. The first electrode is disposed between the stacked structure and the first passive component. The first passive component is electrically connected to the stacked structure through the first electrode.

    Package device
    2.
    发明授权

    公开(公告)号:US11901315B2

    公开(公告)日:2024-02-13

    申请号:US17495821

    申请日:2021-10-07

    CPC classification number: H01L23/642 H01L23/49822 H01L23/49838 H01L28/60

    Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.

    Method for manufacturing electronic device having a seed layer on a substrate

    公开(公告)号:US11789066B2

    公开(公告)日:2023-10-17

    申请号:US17834869

    申请日:2022-06-07

    Inventor: Yeong-E Chen

    CPC classification number: G01R31/2884 G01R31/2831 H01L21/76871 H01L24/06

    Abstract: A method for manufacturing an electronic device includes the following steps. A substrate including a first region and a second region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of first circuit structures disposed on the first region and a plurality of second circuit structures disposed on the second region. The first circuit structures and the second circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the second circuit structures to test the first circuit structures to determine whether the first circuit structures are normal or not.

    Electronic device
    5.
    发明授权

    公开(公告)号:US12205854B2

    公开(公告)日:2025-01-21

    申请号:US18369847

    申请日:2023-09-19

    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.

    Method for manufacturing an electronic device

    公开(公告)号:US11551970B2

    公开(公告)日:2023-01-10

    申请号:US17109101

    申请日:2020-12-01

    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; providing a supporting platform having a plurality of vacuum valves; disposing a substrate on the supporting platform; applying vacuum attraction to a portion of the substrate through a portion of the plurality of vacuum valves, wherein the portion of the substrate corresponding to the vacuum attraction is defined as an attracted region; and performing an exposure on a portion of the attracted region, wherein an area of the attracted region is larger than the basic working area and smaller than an area of the supporting platform.

    MANUFACTURING METHOD OF PACKAGE CIRCUIT

    公开(公告)号:US20220173000A1

    公开(公告)日:2022-06-02

    申请号:US17519540

    申请日:2021-11-04

    Abstract: The embodiments of the disclosure provide a manufacturing method of a package circuit, including the following steps. A circuit structure including a plurality of conductive pads is formed. A liquid crystal layer is formed on the circuit structure. An inspection step is performed, and the inspection step includes determining the conductivity of the conductive pads according to the result of the rotation of a liquid crystal layer oriented with an electric field. In addition, the liquid crystal layer is removed.

    METHOD FOR MANUFACTURING ELECTRONIC DEVICE

    公开(公告)号:US20210341534A1

    公开(公告)日:2021-11-04

    申请号:US16861230

    申请日:2020-04-29

    Inventor: Yeong-E Chen

    Abstract: A method for manufacturing an electronic device includes the following steps. A substrate including a main region and a peripheral region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of chip connection structures disposed on the main region and a plurality of test circuit structures disposed on the peripheral region. The chip connection structures and the test circuit structures are physically separated from each other, and the chip connection structures and the test circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the test circuit structures to test the chip connection structures. A test result is obtained to determine whether a chip is electrically connected to the chip connection structures.

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