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    Continuous time linear equalization for current-mode logic with transformer
    1.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权
    具有变压器电流模式逻辑的连续时间线性均衡

    公开(公告)号：US09325319B1

    公开(公告)日：2016-04-26

    申请号：US14679934

    申请日：2015-04-06

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H03K19/094 ,  H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

    Data rate programming using source degenerated CTLE
    2.
    发明授权
    Data rate programming using source degenerated CTLE 有权
    使用源退化CTLE的数据速率编程

    公开(公告)号：US09225560B1

    公开(公告)日：2015-12-29

    申请号：US14681989

    申请日：2015-04-08

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04L25/06 ,  H04L25/10 ,  H04L25/03 ,  H03K17/687

    CPC classification number: H04L25/03885 ,  H03K17/687 ,  H04B10/58 ,  H04B10/6163 ,  H04L25/03019

    Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 在各种实施例中，本发明提供一种通过改变其负载电阻和源极电阻的电阻值来改变输出频率响应的CML器件。 使用偏置控制电压来调整CML器件的尾部电流，尾电流调节CML器件的输出增益。 还有其它实施例。

    Serializer/deserializer apparatus with loopback configuration and methods thereof
    3.
    发明授权
    Serializer/deserializer apparatus with loopback configuration and methods thereof 有权
    具有环回配置的串行器/解串器设备及其方法

    公开(公告)号：US08964820B2

    公开(公告)日：2015-02-24

    申请号：US14479121

    申请日：2014-09-05

    Applicant: Inphi Corporation

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04B1/38 ,  H04L25/06 ,  H04B3/04

    CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

    Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

    Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

    Continuous time linear equalization for current-mode logic with transformer
    5.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权
    具有变压器电流模式逻辑的连续时间线性均衡

    公开(公告)号：US09537685B2

    公开(公告)日：2017-01-03

    申请号：US15074530

    申请日：2016-03-18

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

    Continuous time linear equalization for current-mode logic with transformer
    6.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权

    公开(公告)号：US09853842B2

    公开(公告)日：2017-12-26

    申请号：US15359338

    申请日：2016-11-22

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H04L25/03 ,  H03K19/094 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Serializer/deserializer apparatus with loopback configuration and methods thereof
    8.
    发明授权
    Serializer/deserializer apparatus with loopback configuration and methods thereof 有权
    具有环回配置的串行器/解串器设备及其方法

    公开(公告)号：US08855176B1

    公开(公告)日：2014-10-07

    申请号：US14256792

    申请日：2014-04-18

    Applicant: INPHI Corporation

    Inventor： Parmanand Mishra ,  Michael S. Harwood

    IPC: H04B1/38 ,  H04L25/06

    CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

    Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

    Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

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