公开(公告)号：US20240345865A1

公开(公告)日：2024-10-17

申请号：US18643932

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20180136971A1

公开(公告)日：2018-05-17

申请号：US15577041

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： YAO ZU DONG ,  KUN TIAN

IPC: G06F9/48 ,  G06F9/455

CPC classification number: G06F9/4856 ,  G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45583

Abstract: Examples may include techniques for virtual machine (VM) migration. Examples may include selecting a VM for live migration from a source node to a destination node, predicting a time period associated with the live migration, and selecting another VM from which allocated source node bandwidth may borrowed to facilitate the live migration within the predicted time.

公开(公告)号：US20170300347A1

公开(公告)日：2017-10-19

申请号：US15516381

申请日：2014-10-08

Applicant: INTEL CORPORATION

Inventor： KUN TIAN ,  YAO ZU DONG

IPC: G06F9/455

CPC classification number: G06F9/455 ,  G06F9/45558 ,  G06F11/1446 ,  G06F11/1461 ,  G06F2009/4557 ,  G06F2009/45595 ,  G06F2201/84

Abstract: Examples may include a determining a checkpointing/delivery policy for primary and secondary virtual machines based on output-packet-similarities. The output-packet-similarities may be based on a comparison of time intervals via which content matched for packets outputted from the primary and secondary virtual machines. A checkpointing/delivery mode may then be selected based, at least in part, on the determined checkpointing/delivery policy.

公开(公告)号：US20180293183A1

公开(公告)日：2018-10-11

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/1027 ,  G06F12/0802

CPC classification number: G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20180143885A1

公开(公告)日：2018-05-24

申请号：US15576075

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： YAO ZU DONG ,  YUNHONG JIANG ,  KUN TIAN

IPC: G06F11/14 ,  H04L1/08 ,  G06F9/54

CPC classification number: G06F11/1471 ,  G06F9/547 ,  G06F11/1482 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/805 ,  G06F2201/82 ,  H04L1/08

Abstract: It includes techniques to provide for reliable primary and secondary containers arranged to separately execute an application that receives request packets for processing by the application. The request packets may be received from a client coupled with a server arranged to host the primary container or the secondary container. The client coupled with the server through a network. Coarse-grained lock-stepping (COLO) methods may be utilized to facilitate in providing the reliable primary and secondary containers.

公开(公告)号：US20230153143A1

公开(公告)日：2023-05-18

申请号：US18097897

申请日：2023-01-17

Applicant: Intel Corporation

Inventor： SHAOPENG HE ,  ANJALI SINGHAI JAIN ,  UTKARSH Y. KAKAIYA ,  YADONG LI ,  ELIEL LOUZOUN ,  KUN TIAN ,  BRADLEY BURRES ,  RORY HARRIS ,  YAN ZHAO

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.

公开(公告)号：US20210056051A1

公开(公告)日：2021-02-25

申请号：US17008991

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20230161615A1

公开(公告)日：2023-05-25

申请号：US18153177

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20190391937A1

公开(公告)日：2019-12-26

申请号：US16453995

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/0802 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/1009

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.