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    MEMORY CELL INCLUDING MULTI-LEVEL SENSING
    1.
    发明申请
    MEMORY CELL INCLUDING MULTI-LEVEL SENSING 审中-公开

    公开(公告)号：US20190043570A1

    公开(公告)日：2019-02-07

    申请号：US15911350

    申请日：2018-03-05

    Applicant: Intel Corporation

    Inventor： Bruce Querbach ,  Christopher Connor

    IPC: G11C13/00 ,  G11C11/408 ,  H03K19/0175 ,  G11C29/12 ,  G11C14/00 ,  G11C11/56

    Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

    ETCH STOP FOR OXIDE SEMICONDUCTOR DEVICES
    4.
    发明公开
    ETCH STOP FOR OXIDE SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240222514A1

    公开(公告)日：2024-07-04

    申请号：US18090056

    申请日：2022-12-28

    Applicant: Intel Corporation

    Inventor： Christopher Connor ,  Vishak Venkatraman ,  Vladimir Nikitin ,  Yasin Kaya

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

    Abstract: An integrated circuit structure includes a first layer comprising a semiconductor material. In an example, the semiconductor material of the layer comprises an oxide semiconductor material (e.g., comprising a metal and oxygen). The integrated circuit structure further includes a second layer above the first layer, where the second layer includes a metal and one of oxygen or nitrogen (e.g., includes aluminum and oxygen). In an example, the second layer is an etch stop layer. In an example, the second layer has a thickness of at most 20 nanometers. The integrated circuit structure further includes a first source or drain terminal and a second source or drain terminal, where each of the first and second source or drain terminals extends through the second layer and is coupled to the first layer. In an example, the integrated circuit structure is a thin film transistor (TFT), where the first layer is a thin film channel structure of the TFT.

    GATE DIELECTRIC FOR THIN FILM OXIDE TRANSISTORS
    5.
    发明申请
    GATE DIELECTRIC FOR THIN FILM OXIDE TRANSISTORS 有权

    公开(公告)号：US20230080212A1

    公开(公告)日：2023-03-16

    申请号：US17476165

    申请日：2021-09-15

    Applicant: Intel Corporation

    Inventor： Christopher Connor ,  James O'Donnell ,  Shailesh Kumar Madisetti

    IPC: H01L29/786 ,  H01L29/66

    Abstract: A thin film transistor (TFT) structure. In an example, the TFT includes a gate electrode, a first layer comprising an oxide semiconductor material, and a second layer between the first layer and the gate electrode. The second layer is crystalline and is in contact with the first layer, and includes zirconium and oxygen. The TFT includes a first contact coupled to the first layer at a first location, and a second contact coupled to the first layer at a second location. In some cases, the second layer further includes hafnium. In some cases, the TFT includes a third layer between of the gate electrode and the second layer, the third layer comprising a metal and oxygen. The gate electrode may also include the metal. In some cases, hydrogen is present at an interface between the gate electrode and the second layer.

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