公开(公告)号：US20200098698A1

公开(公告)日：2020-03-26

申请号：US16143212

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Richard PATTEN ,  David O'SULLIVAN ,  Georg SEIDEMANN ,  Bernd WAIDHAS

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.

公开(公告)号：US20230343766A1

公开(公告)日：2023-10-26

申请号：US18217000

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： David O'SULLIVAN ,  Georg SEIDEMANN ,  Richard PATTEN ,  Bernd WAIDHAS

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L23/3114 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20250167183A1

公开(公告)日：2025-05-22

申请号：US19034153

申请日：2025-01-22

Applicant: Intel Corporation

Inventor： David O'SULLIVAN ,  Georg SEIDEMANN ,  Richard PATTEN ,  Bernd WAIDHAS

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20230317621A1

公开(公告)日：2023-10-05

申请号：US17707708

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  David O'SULLIVAN ,  Georg SEIDEMANN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L24/08 ,  H01L23/5383 ,  H01L23/15 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/80 ,  H01L23/49811 ,  H01L21/486 ,  H01L2224/08225 ,  H01L2224/05647 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to semiconductor packages that include a glass interposer that includes electrically conductive through glass vias that extend through the interposer. One or more dies may be hybrid bonded to a first side of the glass interposer. In embodiments, the second side of the glass interposer may include a redistribution layer that is electrically coupled with the one or more dies through the through glass vias. Other embodiments may be described and/or claimed.