公开(公告)号：US20180005965A1

公开(公告)日：2018-01-04

申请号：US15201375

申请日：2016-07-01

申请人： Intel Corporation

发明人： Yu Amos ZHANG ,  Jihwan KIM ,  Ajay BALANKUTTY ,  Anupriya SRIRAMULU ,  MD. Mohiuddin MAZUMDER ,  Frank O'MAHONY ,  Zuoguo WU ,  Kemal AYGUN

IPC分类号： H01L23/64 ,  H01L23/66 ,  H01L27/02 ,  H02H9/04

CPC分类号： H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

摘要： Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US20160241249A1

公开(公告)日：2016-08-18

申请号：US15025226

申请日：2013-11-19

申请人： INTEL CORPORATION

发明人： Ganesh BALAMURUGAN ,  Mozhgan MANSURI ,  Sami HYVONEN ,  Bryan K. CASPER ,  Frank O'MAHONY

IPC分类号： H03L7/00 ,  H04B1/04 ,  H03K5/156 ,  H04L25/03

CPC分类号： H03L7/00 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/08 ,  H04B1/04 ,  H04L25/03

摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.

摘要翻译： 描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。