公开(公告)号：US20180005965A1

公开(公告)日：2018-01-04

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Jihwan KIM ,  Ajay BALANKUTTY ,  Anupriya SRIRAMULU ,  MD. Mohiuddin MAZUMDER ,  Frank O'MAHONY ,  Zuoguo WU ,  Kemal AYGUN

IPC: H01L23/64 ,  H01L23/66 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US20180331036A1

公开(公告)日：2018-11-15

申请号：US15773950

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC: H01L23/528 ,  H01L23/66 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00 ,  H01R13/6471

CPC classification number: H01L23/5286 ,  H01L21/4857 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/17 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R13/6471 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US20190148227A1

公开(公告)日：2019-05-16

申请号：US16098662

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Kemal AYGUN

IPC: H01L21/768 ,  H01L23/50 ,  H01L23/522

Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.

公开(公告)号：US20180331035A1

公开(公告)日：2018-11-15

申请号：US15773896

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Mathew J. MANUSHAROW ,  Kemal AYGUN ,  Mohiuddin MAZUMDER

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H05K1/02 ,  H01R13/6471

Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.

公开(公告)号：US20180374804A1

公开(公告)日：2018-12-27

申请号：US15774958

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01P3/06 ,  H01P11/00

Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20180331043A1

公开(公告)日：2018-11-15

申请号：US15774257

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Zhiguo QIAN ,  Kemal AYGUN ,  Yidnekachew S. MEKONNEN ,  Gregorio R. MURTAGIAN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Jeff C. MORRISS

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/552

CPC classification number: H01L23/5384 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/00 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.