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公开(公告)号:US20190295953A1
公开(公告)日:2019-09-26
申请号:US15933934
申请日:2018-03-23
申请人: Intel Corporation
发明人: Mayue XIE , Jong-Ru GUO , Zhiguo QIAN , Zuoguo WU
IPC分类号: H01L23/538 , H01L23/58 , H01L25/065
摘要: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.
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公开(公告)号:US20180005965A1
公开(公告)日:2018-01-04
申请号:US15201375
申请日:2016-07-01
申请人: Intel Corporation
发明人: Yu Amos ZHANG , Jihwan KIM , Ajay BALANKUTTY , Anupriya SRIRAMULU , MD. Mohiuddin MAZUMDER , Frank O'MAHONY , Zuoguo WU , Kemal AYGUN
CPC分类号: H01L23/645 , H01L23/66 , H01L27/0248 , H01L27/0288 , H02H9/046
摘要: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.
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公开(公告)号:US20220206064A1
公开(公告)日:2022-06-30
申请号:US17133659
申请日:2020-12-24
申请人: Intel Corporation
发明人: Zhen ZHOU , Renzhi LIU , Jong-Ru GUO , Kenneth P. FOUST , Jason A. MIX , Kai XIAO , Zuoguo WU , Daqiao DU
IPC分类号: G01R31/302 , H01P3/08 , H01Q9/16 , H04B5/02 , G01R31/28 , G01R31/303
摘要: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.
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公开(公告)号:US20190045622A1
公开(公告)日:2019-02-07
申请号:US15817098
申请日:2017-11-17
申请人: Intel Corporation
发明人: Jun LIAO , Zhen ZHOU , James A. McCALL , Jong-Ru GUO , Xiang LI , Yunhui CHU , Zuoguo WU
摘要: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.
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公开(公告)号:US20170163286A1
公开(公告)日:2017-06-08
申请号:US15039544
申请日:2013-12-26
申请人: Intel Corporation
CPC分类号: H03M13/11 , G06F13/36 , G06F13/385 , G06F13/4068 , G06F13/4282 , G06F2213/0026
摘要: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
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