公开(公告)号：US20240186127A1

公开(公告)日：2024-06-06

申请号：US18399237

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Ilya V. Karpov ,  Aaron A. Budrevich ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Dan S. Lavric

IPC: H01J37/34 ,  C23C14/34 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01J37/3426 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/456 ,  H01J2237/332

Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. Sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopant is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US20240105588A1

公开(公告)日：2024-03-28

申请号：US17935999

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Ilya V. Karpov ,  Shafaat Ahmed ,  Matthew V. Metz ,  Darren Anthony Denardis ,  Nafees Aminul Kabir ,  Tristan A. Tronic

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53223

Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L29/167

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US20230420246A1

公开(公告)日：2023-12-28

申请号：US17847625

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Ilya V. Karpov ,  Aaron A. Budrevich ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Dan S. Lavric

IPC: H01L21/02 ,  H01L21/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02266 ,  H01L29/785 ,  H01L29/66803 ,  H01L21/24

Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. A region including metals and semiconductor materials is between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopants is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region, and wherein the section of the source or drain region is at a distance of at most 5 nanometers (nm) from the region.