公开(公告)号：US20240006494A1

公开(公告)日：2024-01-04

申请号：US17856206

申请日：2022-07-01

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/41733 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656

摘要： Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

公开(公告)号：US12046654B2

公开(公告)日：2024-07-23

申请号：US16912118

申请日：2020-06-25

申请人： Intel Corporation

发明人： Dan S. Lavric ,  Glenn A. Glass ,  Thomas T. Troeger ,  Suresh Vishwanath ,  Jitendra Kumar Jha ,  John F. Richards ,  Anand S. Murthy ,  Srijit Mukherjee

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

申请人： Intel Corporation

发明人： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

摘要： Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

申请人： Intel Corporation

发明人： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

摘要： Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

公开(公告)号：US12119387B2

公开(公告)日：2024-10-15

申请号：US17033471

申请日：2020-09-25

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Nazila Haratipour ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Jitendra Kumar Jha ,  Matthew V. Metz ,  Mengcheng Lu ,  Anand S. Murthy ,  Koustav Ganguly ,  Ryan Keech ,  Glenn A. Glass ,  Arnab Sen Gupta

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20240006488A1

公开(公告)日：2024-01-04

申请号：US17856620

申请日：2022-07-01

申请人： Intel Corporation

发明人： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  David Kohen ,  Natalie Briggs ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC分类号： H01L29/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/033

CPC分类号： H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L21/0332

摘要： In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

申请人： Intel Corporation

发明人： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC分类号： H01L21/768 ,  H01L29/49

CPC分类号： H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

摘要： Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

申请人： Intel Corporation

发明人： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC分类号： H01L29/78 ,  H01L29/167

CPC分类号： H01L29/785 ,  H01L29/167

摘要： Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.