公开(公告)号：US20240030067A1

公开(公告)日：2024-01-25

申请号：US18374976

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76849 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/517 ,  H01L29/78 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/665 ,  H01L29/16 ,  H01L29/456 ,  H01L21/28123 ,  H01L21/28562 ,  H01L23/535 ,  H01L2029/7858 ,  H01L29/495 ,  H01L2924/0002

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20200251387A1

公开(公告)日：2020-08-06

申请号：US16819590

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/285 ,  H01L21/28 ,  H01L29/45 ,  H01L29/16 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/283 ,  H01L29/78 ,  H01L29/49

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20230154793A1

公开(公告)日：2023-05-18

申请号：US18098029

申请日：2023-01-17

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76849 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/517 ,  H01L29/78 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/665 ,  H01L29/16 ,  H01L29/456 ,  H01L21/28123 ,  H01L21/28562 ,  H01L23/535 ,  H01L2029/7858 ,  H01L29/495 ,  H01L2924/0002

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20210134673A1

公开(公告)日：2021-05-06

申请号：US17147423

申请日：2021-01-12

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20160155815A1

公开(公告)日：2016-06-02

申请号：US14998092

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/16 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.