公开(公告)号：US10163863B2

公开(公告)日：2018-12-25

申请号：US15375112

申请日：2016-12-11

Applicant: INTEL CORPORATION

Inventor： John Guzek

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US20180012871A1

公开(公告)日：2018-01-11

申请号：US15711880

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H01L21/683 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US20190081023A1

公开(公告)日：2019-03-14

申请号：US16189513

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US20170125385A1

公开(公告)日：2017-05-04

申请号：US15375112

申请日：2016-12-11

Applicant: INTEL CORPORATION

Inventor： John Guzek

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US20150357312A1

公开(公告)日：2015-12-10

申请号：US14831250

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括在电镀材料中形成一个空腔以保持模具，将模具连接到空腔中，形成与模具相邻的电介质材料，在邻近模具的电介质材料中形成通孔，在通孔中形成PoP焊盘，形成互连 在通孔中，然后移除电镀材料以暴露PoP焊盘和裸片，其中，模具设置在PoP焊盘上方。

公开(公告)号：US09832860B2

公开(公告)日：2017-11-28

申请号：US14498958

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert Starkston ,  John Guzek ,  Patrick Nardi ,  Keith Jones ,  Javier Soto Gonzalez

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H01L23/16 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/10977 ,  H05K2201/2009

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

公开(公告)号：US10541232B2

公开(公告)日：2020-01-21

申请号：US16189513

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L21/56

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

公开(公告)号：US09553075B2

公开(公告)日：2017-01-24

申请号：US14831250

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括在电镀材料中形成一个空腔以保持模具，将模具连接到空腔中，形成与模具相邻的电介质材料，在邻近模具的电介质材料中形成通孔，在通孔中形成PoP焊盘，形成互连 在通孔中，然后移除电镀材料以暴露PoP焊盘和裸片，其中，模具设置在PoP焊盘上方。

公开(公告)号：US09147669B2

公开(公告)日：2015-09-29

申请号：US14254474

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： John Guzek

IPC: H01L23/02 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/821 ,  H01L2224/8234 ,  H01L2224/8236 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括在电镀材料中形成一个空腔以保持模具，将模具连接到空腔中，形成与模具相邻的电介质材料，在邻近模具的电介质材料中形成通孔，在通孔中形成PoP焊盘，形成互连 在通孔中，然后移除电镀材料以暴露PoP焊盘和裸片，其中，模具设置在PoP焊盘上方。