公开(公告)号：US20240222182A1

公开(公告)日：2024-07-04

申请号：US18147515

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Amey Anant Apte ,  Mukul Renavikar

IPC: H01L21/683 ,  C09J7/24 ,  C09J7/29 ,  C09J7/38 ,  C09J11/04 ,  H01L23/60

CPC classification number: H01L21/6836 ,  C09J7/241 ,  C09J7/29 ,  C09J7/385 ,  C09J11/04 ,  H01L23/60 ,  C09J2203/326 ,  C09J2301/408 ,  C09J2400/243 ,  C09J2423/006 ,  C09J2433/00 ,  C09J2463/008 ,  H01L2221/68377 ,  H01L2221/68386

Abstract: The disclosure is directed to a silicon bridge die package, a dicing-die attach film structure and a method for silicon processing including a silicon bridge die package including at least two silicon die incorporating a plurality of integrated circuits, an embedded multi-die interconnect bridge coupled to the at least two silicon die, a dicing-die attach film (DDAF) structure coupled to a silicon wafer, an electro-static discharge (ESD) preventative within the DDAF structure to prevent static charge within the DDAF structure, and an auxetic material disposed within the DDAF structure configured to prevent dicing errors. A method for preparing a silicon die for singulation includes applying an auxetic material with an ESD preventative additive to an organic resin to form a DDAF, combining the DDAF with an acrylic adhesive and a polyolefin base film, and mounting the DDAF to the silicon die.

公开(公告)号：US11817364B2

公开(公告)日：2023-11-14

申请号：US16017582

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Mukul Renavikar

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L24/06 ,  H01L24/09 ,  H01L24/17 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/15311

Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

公开(公告)号：US20250128362A1

公开(公告)日：2025-04-24

申请号：US18492371

申请日：2023-10-23

Applicant: Intel Corporation

Inventor： Rui Zhang ,  Jiaqi Wu ,  Brian Franco ,  Xiao Lu ,  Mukul Renavikar

IPC: B23K35/26 ,  B23K35/02 ,  B23K103/08 ,  C22C13/02

Abstract: Solder materials and microelectronic devices and systems deploying the solder materials are discussed. The solder material includes a bulk material of tin and bismuth and particles interspersed in the tin and bismuth bulk material. The particles are a metal other than tin and bismuth, and an intermetallic compound is formed around the particles. The intermetallic compound includes the metal of the particles and tin or bismuth. The solder materials are deployed as interconnect structures to interconnect components, such as electrically coupling an integrated circuit package to a motherboard.