公开(公告)号：US09806193B2

公开(公告)日：2017-10-31

申请号：US15250836

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Titash Rakshit ,  Martin Giles ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L21/70 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

公开(公告)号：US20160372574A1

公开(公告)日：2016-12-22

申请号：US15219193

申请日：2016-07-25

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/80 ,  H01L29/51 ,  H01L29/778 ,  H01L29/78 ,  H01L29/15 ,  H01L29/417

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

公开(公告)号：US09450092B2

公开(公告)日：2016-09-20

申请号：US14938812

申请日：2015-11-11

Applicant: Intel Corporation

Inventor： Titash Rakshit ,  Martin Giles ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L21/70 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

公开(公告)号：US09035387B2

公开(公告)日：2015-05-19

申请号：US14089101

申请日：2013-11-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7855 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提高多栅极器件性能的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20150021553A1

公开(公告)日：2015-01-22

申请号：US14507044

申请日：2014-10-06

Applicant: Intel Corporation

Inventor： ANNALISA CAPPELLANI ,  KELIN J. KUHN ,  RAFAEL RIOS ,  Titash Rakshit ,  Sivakumar Mudanai

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract translation: 无连接累积模式（JAM）半导体器件通过JAM半导体的突出特征之下的反向偏压带从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。

公开(公告)号：US10084058B2

公开(公告)日：2018-09-25

申请号：US15219193

申请日：2016-07-25

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/15 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/80 ,  H01L29/165 ,  H01L29/51 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

公开(公告)号：US20160064562A1

公开(公告)日：2016-03-03

申请号：US14938812

申请日：2015-11-11

Applicant: Intel Corporation

Inventor： Titash Rakshit ,  Martin Giles ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

公开(公告)号：US08853741B2

公开(公告)日：2014-10-07

申请号：US13964696

申请日：2013-08-12

Applicant: Intel Corporation

Inventor： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar Mudanai

IPC: H01L29/205 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract translation: 通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。

公开(公告)号：US09595581B2

公开(公告)日：2017-03-14

申请号：US14789856

申请日：2015-07-01

Applicant: Intel Corporation

Inventor： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L27/12 ,  H01L27/092 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。