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公开(公告)号：US12277985B2
公开(公告)日：2025-04-15
申请号：US17390425
申请日：2021-07-30
Applicant: Intel Corporation
Inventor： William K. Waller , Dhruval J. Patel , Xiannan Di
Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.
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2.发明公开公开(公告)号：US20230282259A1
公开(公告)日：2023-09-07
申请号：US17688357
申请日：2022-03-07
Applicant: Intel Corporation
Inventor： William K. Waller
CPC classification number: G11C8/10 , G11C8/14 , G11C8/08 , G11C7/18 , G11C7/12 , G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: In one embodiment, a non-volatile memory apparatus includes a plurality of memory tiles that each include a set of main memory tiles arranged in rows and columns and a set of row termination tiles at the ends of the rows and a set of column termination tiles at the ends of the columns. Each main memory tile includes a set of address lines orthogonal to one another, memory cells between the overlapping areas of the orthogonal address lines, address line driver circuitry, and circuitry to selectively couple the address line driver circuitry to an address line decoder circuit of an adjacent memory tile to activate address lines in the main memory tile.
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Patent Agency Ranking
3.发明授权公开(公告)号：US12237040B2
公开(公告)日：2025-02-25
申请号：US17468210
申请日：2021-09-07
Applicant: Intel Corporation
Inventor： Sourabh Dongaonkar , Chetan Chauhan , Jawad B. Khan , Sandeep K. Guliani , William K. Waller
Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.
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公开(公告)号：US20230393978A1
公开(公告)日：2023-12-07
申请号：US17831236
申请日：2022-06-02
Applicant: Intel Corporation
Inventor： William K. Waller , Sarang Agrawal
IPC: G06F12/06
CPC classification number: G06F12/06 , G11C16/0483
Abstract: A memory device may include a level shifter circuit that drives multiples half latch circuits. The half latch circuits may each include a p-channel transistor whose source is connected to a first voltage and whose gate is to receive addressing signals, a first inverter circuit connected between the drain of the p-channel transistor and a second voltage and whose input is connected to an output of the level shifter circuit, a second inverter circuit connected between the second voltage and a third voltage to receive an output of the first inverter circuit as input, a third inverter circuit connected between the second and third voltages to receive an output of the second inverter circuit as input, and an n-channel transistor connected between the output of the third inverter circuit and the input of the second inverter circuit, wherein a gate of the n-channel transistor is connected to a bias voltage.
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公开(公告)号：US20230092848A1
公开(公告)日：2023-03-23
申请号：US17482578
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： William K. Waller
Abstract: In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.
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公开(公告)号：US20230033277A1
公开(公告)日：2023-02-02
申请号：US17390425
申请日：2021-07-30
Applicant: Intel Corporation
Inventor： William K. Waller , Dhruval J. Patel , Xiannan Di
Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.
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公开(公告)号：US12254946B2
公开(公告)日：2025-03-18
申请号：US17482578
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： William K. Waller
Abstract: In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.
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