公开(公告)号：US20170338105A1

公开(公告)日：2017-11-23

申请号：US15528329

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Yan A. BORODOVSKY ,  Charles H. WALLACE ,  Paul A. NYHUS

IPC: H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  G03F7/11 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/0277 ,  G03F7/093 ,  G03F7/11 ,  G03F7/2059 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.

公开(公告)号：US20210358713A1

公开(公告)日：2021-11-18

申请号：US17388945

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US20190013175A1

公开(公告)日：2019-01-10

申请号：US16069708

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Gabriele CANZI

IPC: H01J37/04 ,  H01J37/317 ,  H01J37/147 ,  H01J37/20

CPC classification number: H01J37/045 ,  H01J37/147 ,  H01J37/20 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/20214 ,  H01J2237/31766 ,  H01L21/0273 ,  H01L21/76802 ,  H01L29/66795

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.

公开(公告)号：US20190164723A1

公开(公告)日：2019-05-30

申请号：US16323128

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

IPC: H01J37/30 ,  H01L21/033 ,  H01J37/317

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.