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    FILL PATTERN TO ENHANCE EBEAM PROCESS MARGIN
    1.
    发明申请
    FILL PATTERN TO ENHANCE EBEAM PROCESS MARGIN 审中-公开

    公开(公告)号：US20190164723A1

    公开(公告)日：2019-05-30

    申请号：US16323128

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

    IPC: H01J37/30 ,  H01L21/033 ,  H01J37/317

    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

    UNIDIRECTIONAL METAL ON LAYER WITH EBEAM
    2.
    发明申请
    UNIDIRECTIONAL METAL ON LAYER WITH EBEAM 审中-公开
    带EBEAM的单层金属

    公开(公告)号：US20170077029A1

    公开(公告)日：2017-03-16

    申请号：US15122396

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON ,  Yan A. BORODOVSKY ,  Mark C. PHILLIPS

    IPC: H01L23/528 ,  H01L27/11 ,  H01L21/768 ,  H01L27/02

    CPC classification number: H01L23/5283 ,  H01J37/045 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76886 ,  H01L27/0207 ,  H01L27/11

    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.

    Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，集成电路的金属化层的布局包括具有第一宽度和第一间距的多个单向线并与第一方向平行的第一区域。 布局还包括具有第二宽度和第二间距的多个单向线并且与第一方向平行的第二区域，第二宽度和第二间距分别与第一宽度和第一间距不同的第二区域。 布局还包括具有第三宽度和第三间距的多个单向线并且与第一方向平行的第三区域，第三宽度和第三间距不同于第一和第二宽度并且不同于第一和第二间距 。

    EBEAM ALIGN ON THE FLY
    3.
    发明申请
    EBEAM ALIGN ON THE FLY 审中-公开
    飞行中的EBEAM对齐

    公开(公告)号：US20170076967A1

    公开(公告)日：2017-03-16

    申请号：US15122792

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

    IPC: H01L21/68

    CPC classification number: H01L21/682 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/24578 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.

    Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，位于电子束工具的台上的晶片的实时对准的方法涉及从电子束工具的电子束列的电子束列中收集来自晶片的底层图案化特征的反向散射电子， 扫描舞台。 收集由放置在电子束柱底部的电子检测器进行。 该方法还涉及基于收集来执行阶段相对于电子束列的对准的线性校正。

    FILL PATTERN TO ENHANCE EBEAM PROCESS MARGIN
    7.
    发明申请
    FILL PATTERN TO ENHANCE EBEAM PROCESS MARGIN 有权

    公开(公告)号：US20210358713A1

    公开(公告)日：2021-11-18

    申请号：US17388945

    申请日：2021-07-29

    Applicant: Intel Corporation

    Inventor： Shakul TANDON ,  Mark C. PHILLIPS ,  Shem O. OGADHOH ,  John A. SWANSON

    IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

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