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1.发明授权Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores 有权使用一系列系数值和当前活动核心数量，基于不同的多项式方程计算处理器的动态可变最大工作电压值公开(公告)号：US09335803B2
公开(公告)日：2016-05-10
申请号：US13768633
申请日：2013-02-15
Applicant: Intel Corporation
Inventor： Zhiguo Wang , David J. Ayers , Srikanth Balasubramanian , Sukirti Gupta , Stefan Rusu , Stephen M. Ramey
CPC classification number: G06F1/26 , G06F1/206 , G06F1/32 , G06F1/3206 , G06F1/3296 , G06F9/50 , G06F9/5094 , Y02D10/172
Abstract: In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括电压计算逻辑以至少部分地基于多个系数值来计算与多个核的多个活动核心数量相关联的多个最大工作电压值。 以这种方式，处理器可以根据活动核心的数量在不同的最大工作电压下工作。 描述和要求保护其他实施例。
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公开(公告)号：US08892929B2
公开(公告)日：2014-11-18
申请号：US13780103
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。
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公开(公告)号：US09405358B2
公开(公告)日：2016-08-02
申请号：US14515694
申请日：2014-10-16
Applicant: Intel Corporation
Inventor： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。
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