公开(公告)号：US20200249271A1

公开(公告)日：2020-08-06

申请号：US16265661

申请日：2019-02-01

Applicant: Intel Corporation

Inventor： Suriya Ashok Kumar ,  Ketul B. Sutaria ,  Stephen M. Ramey

IPC: G01R31/28 ,  H01L27/092 ,  H03K3/354 ,  H03K21/38 ,  G01R31/00

Abstract: Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.

公开(公告)号：US10355005B2

公开(公告)日：2019-07-16

申请号：US15576269

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young ,  Stephen M. Ramey

IPC: H01L27/11521 ,  G11C16/04 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11526 ,  H01L29/66 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.

公开(公告)号：US09335803B2

公开(公告)日：2016-05-10

申请号：US13768633

申请日：2013-02-15

Applicant: Intel Corporation

Inventor： Zhiguo Wang ,  David J. Ayers ,  Srikanth Balasubramanian ,  Sukirti Gupta ,  Stefan Rusu ,  Stephen M. Ramey

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/172

Abstract: In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括电压计算逻辑以至少部分地基于多个系数值来计算与多个核的多个活动核心数量相关联的多个最大工作电压值。 以这种方式，处理器可以根据活动核心的数量在不同的最大工作电压下工作。 描述和要求保护其他实施例。

公开(公告)号：US11099232B2

公开(公告)日：2021-08-24

申请号：US16265661

申请日：2019-02-01

Applicant: Intel Corporation

Inventor： Suriya Ashok Kumar ,  Ketul B. Sutaria ,  Stephen M. Ramey

IPC: G01R31/28 ,  H03K3/03 ,  G01R31/00

Abstract: Various embodiments provide a health monitor circuit including an n-type sensor to determine a first health indicator associated with n-type transistors of a circuit block and a p-type sensor to determine a second health indicator associated with p-type transistors of the circuit block. The n-type sensor and p-type sensor may be on a same die as the circuit block. The health monitor circuit may further include a control circuit to adjust one or more operating parameters, such as operating voltage and/or operating frequency, for the circuit block based on the first and second health indicators. Other embodiments may be described and claimed.