公开(公告)号：US20240332071A1

公开(公告)日：2024-10-03

申请号：US18129704

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Alireza Narimannezhad ,  Vladislav Kamysbayev ,  Xiaoye Qin ,  Sunzida Ferdous ,  Reken Patel

IPC: H01L21/768 ,  C23C16/40 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76834 ,  C23C16/401 ,  C23C16/45538 ,  C23C16/50 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/0228 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53257

Abstract: A low-leakage oxide dielectric material with high elastic modulus is deposited directly upon an oxidizable feature with a polycyclic PE-ALD process that limits the formation of an oxide on the feature. A precursor of one or more constituents, such as silicon, may be deposited upon a workpiece during a deposition phase, and the absorbed precursor(s) may be oxidized during a first oxidation phase under more conservative conditions until a first film thickness is achieved. Subsequently, absorbed precursor(s) may be oxidized during a second oxidation phase under more aggressive conditions to arrive at a total film thickness. Transistor contact metal, which may provide local interconnection between source or drain terminals of multiple transistors, may maintain high electrical conductivity after being electrically insulated with such a low-leakage film.

公开(公告)号：US20240222447A1

公开(公告)日：2024-07-04

申请号：US18090048

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Reken Patel ,  Conor P. Puls ,  Krishna Ganesan ,  Akitomo Matsubayashi ,  Diana Ivonne Paredes ,  Sunzida Ferdous ,  Brian Greene ,  Lateef Uddin Syed ,  Kyle T. Horak ,  Lin Hu ,  Anupama Bowonder ,  Swapnadip Ghosh ,  Amritesh Rai ,  Shruti Subramanian ,  Gordon S. Freeman

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.