公开(公告)号：US20240222520A1

公开(公告)日：2024-07-04

申请号：US18090822

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE

IPC: H01L29/786 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L29/78696 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/0673 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

公开(公告)号：US20240222271A1

公开(公告)日：2024-07-04

申请号：US18090828

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.

公开(公告)号：US20230317145A1

公开(公告)日：2023-10-05

申请号：US17711286

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Rajabali KODURI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094

Abstract: Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. In one embodiment, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

公开(公告)号：US20230315331A1

公开(公告)日：2023-10-05

申请号：US17711394

申请日：2022-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Rajabali KODURI

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.

公开(公告)号：US20230005526A1

公开(公告)日：2023-01-05

申请号：US17943044

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: G11C11/406 ,  H01L25/065 ,  H01L25/18

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240103304A1

公开(公告)日：2024-03-28

申请号：US17954286

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02F1/025

CPC classification number: G02F1/025

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

公开(公告)号：US20240103216A1

公开(公告)日：2024-03-28

申请号：US17954292

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

公开(公告)号：US20230005921A1

公开(公告)日：2023-01-05

申请号：US17943038

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: H01L27/108 ,  G11C5/06

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

公开(公告)号：US20240224504A1

公开(公告)日：2024-07-04

申请号：US18089957

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Pushkar RANADE ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H10B12/00

CPC classification number: H01L27/1082 ,  H01L27/10873 ,  H01L29/1608

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.