公开(公告)号：US11735521B2

公开(公告)日：2023-08-22

申请号：US17510190

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni ,  Vincent E. Dorgan ,  Uddalak Bhattacharya

IPC: H10B20/20 ,  H01L23/525 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L23/5252 ,  H01L27/0251 ,  H01L29/7833 ,  H10B20/20

Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

公开(公告)号：US20220253285A1

公开(公告)日：2022-08-11

申请号：US17730011

申请日：2022-04-26

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Clifford Lu Ong ,  Dmitri E. Nikonov ,  Ian A. Young ,  Eric A. Karl

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/22 ,  G06N3/04

Abstract: An analog multiplication circuit includes switched capacitors to multiply digital operands in an analog representation and output a digital result with an analog-to-digital convertor. The capacitors are arranged with a capacitance according to the respective value of the digital bit inputs. To perform the multiplication, the capacitors are selectively charged according to the first operand of the multiplication. The capacitors are then connected to a common interconnect for charge sharing across the capacitors, averaging the charge according to the charge determined by the first operand. The capacitor are then maintained or discharged according to a second operand, such that the remaining charge represents a number of “copies” of the averaged charge. The capacitors are then averaged and output for conversion by an analog-to-digital convertor. This circuit may be repeated to construct a multiply-and-accumulate circuit by combining charges from several such multiplication circuits.

公开(公告)号：US11189564B2

公开(公告)日：2021-11-30

申请号：US15943541

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni ,  Vincent E. Dorgan ,  Uddalak Bhattacharya

IPC: H01L23/525 ,  H01L29/78 ,  H01L27/112 ,  H01L27/02

Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

公开(公告)号：US20210098059A1

公开(公告)日：2021-04-01

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/56 ,  G11C7/10 ,  G06F3/06

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US12009026B2

公开(公告)日：2024-06-11

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/54 ,  G06F3/06 ,  G11C7/10 ,  G11C11/56 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/1051 ,  G11C7/1096 ,  G11C7/06 ,  G11C7/222

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US11276697B2

公开(公告)日：2022-03-15

申请号：US15943548

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Sarvesh H. Kulkarni

IPC: H01L27/112 ,  H01L23/525 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78

Abstract: Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a semiconductor well, a source area and a drain area next to the semiconductor well, a gate electrode, and a base terminal. The gate electrode may be coupled to the base terminal, hence forming a floating body MOSFET. A junction may exist between the drain area and the semiconductor well. A first resistance may exist between the source area and the drain area through the semiconductor well. A programming operation may be performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230162772A1

公开(公告)日：2023-05-25

申请号：US17706124

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Zhanping Chen ,  Sarvesh Kulkarni ,  Rachael Parker ,  Jyothi Bhaskarr Velamala

IPC: G11C7/24 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C7/24 ,  G11C17/16 ,  G11C17/18

Abstract: Hot carrier injection (HCI) may be used to provide various improvements for one-time programmable (OTP) read-only memory (ROM) or physical unclonable function (PUF) circuits. HCI may be used to write a memory bit (e.g., logical 0 or 1), which may be used in OTP ROM. HCI may be used to provide improved programmable ROM (PROM) memory devices, such as to facilitate programming or to increase sensing window. HCI may also be used to write a memory bit in a PUF circuit. HCI may provide a cross-foundry portable PUF circuit that has an associated adjustable bit error rate (BER), which may be used to secure root key generation, or may be used to provide a unique identification (ID) for fuse replacement.