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公开(公告)号：US10424727B2
公开(公告)日：2019-09-24
申请号：US16364794
申请日：2019-03-26
摘要： Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
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2.发明申请公开(公告)号：US20180240967A1
公开(公告)日：2018-08-23
申请号：US15956376
申请日：2018-04-18
CPC分类号： H01L43/08 , B81C2201/0132 , B81C2201/0142 , B81C2201/0143 , G11C11/161 , G11C2211/5615 , H01L21/31105 , H01L43/02 , H01L43/10 , H01L43/12
摘要： A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.
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公开(公告)号：US20170005260A1
公开(公告)日：2017-01-05
申请号：US14949267
申请日：2015-11-23
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1659 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
摘要翻译： 技术涉及线性磁阻随机存取存储器（MRAM）装置。 线性磁性隧道结结构包括在自由层顶部的非磁性隧道势垒和非磁性隧道势垒顶部的参考层，其中线性磁性隧道结结构处于一条直线上。 底部触点通过列空间彼此分离，同时多个底部触点与线性磁性隧道结结构自对准，使得多个底部触点与线性磁性隧道结结构线并联。 底部触点邻接线性磁隧道结结构的底部。 通过使自由层的非导电部分隔离底部触点和自由层之间的各个界面来形成MRAM器件。 MRAM器件形成在线性磁隧道结结构的线中。
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4.发明申请INJECTION PILLAR DEFINITION FOR LINE MRAM BY A SELF-ALIGNED SIDEWALL TRANSFER 有权通过自对准的平台转移线MRAM的注射柱定义公开(公告)号：US20160380027A1
公开(公告)日：2016-12-29
申请号：US14920538
申请日：2015-10-22
CPC分类号： H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
摘要： A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.
摘要翻译： 技术涉及MRAM系统。 保形膜覆盖形成在上部材料中的沟槽。 上部材料覆盖基板中的导电岛。 选择性地蚀刻保形膜以在沟槽上留下侧壁。 侧壁被蚀刻成垂直的柱，其自对准并且直接位于下面的导电岛的顶部。 将填充材料沉积并平坦化以留下垂直柱的暴露顶部。 MTJ元件形成在填充材料的顶部和垂直柱的暴露的顶部。 将MTJ元件图案化成对应于垂直列的线，并且每条线具有与其中一个垂直列自对准的线MTJ元件。 线路MRAM器件通过将MTJ元件图案化成线。 线路MRAM设备中的每一个分别包括与一个垂直列自对准的线MTJ元件。
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5.发明授权Thermally assisted MRAM with a multilayer encapsulant for low thermal conductivity 有权热辅助MRAM具有低导热性的多层密封剂公开(公告)号：US09054300B2
公开(公告)日：2015-06-09
申请号：US13971518
申请日：2013-08-20
摘要： A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.
摘要翻译： 提供了一种用于热辅助磁阻随机存取存储器件的技术。 形成磁性隧道结。 形成具有顶部接触电极和底部接触电极的接触布线。 接触布线提供写入偏压以加热磁性隧道结。 多层电介质密封剂构造成将热量保持在磁性隧道结内。
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公开(公告)号：US08951811B2
公开(公告)日：2015-02-10
申请号：US13970764
申请日：2013-08-20
CPC分类号： H01L43/12 , B82Y10/00 , B82Y99/00 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C19/0808 , H01F1/0072 , H01F10/3263 , H01L29/0673 , H01L43/08
摘要： A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
摘要翻译： 存储器件包括耦合第一和第二纳米线的第一纳米线，第二纳米线和磁性隧道结器件。
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公开(公告)号：US10326074B2
公开(公告)日：2019-06-18
申请号：US15671847
申请日：2017-08-08
摘要： Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
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公开(公告)号：US09793471B2
公开(公告)日：2017-10-17
申请号：US15088849
申请日：2016-04-01
CPC分类号： H01L43/12 , B82Y40/00 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L43/08
摘要： Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
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公开(公告)号：US09082963B2
公开(公告)日：2015-07-14
申请号：US14556967
申请日：2014-12-01
CPC分类号： H01L43/12 , B82Y40/00 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L43/08
摘要： Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
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公开(公告)号：US09070868B2
公开(公告)日：2015-06-30
申请号：US13909506
申请日：2013-06-04
摘要： A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.
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