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1.发明申请A METHOD, APPARATUS AND CIRCUIT FOR LATCHUP SUPPRESSION IN A GATE-ARRAY ASIC ENVIRONMENT 失效门阵列环境中的锁定抑制的方法，装置和电路公开(公告)号：US20040262643A1
公开(公告)日：2004-12-30
申请号：US10604176
申请日：2003-06-30
发明人： Steven H. Voldman
IPC分类号： H02H003/20
CPC分类号： H01L27/0921 , H01L27/11807
摘要： An integrated circuit having a substrate (10), a power rail (18, 20), a sea of gates (12), and a latchup control isolation network electrically coupled to substrate (10). The latchup control isolation network electrically isolates sea of gates (12) from power rail (18, 20). In another embodiment, an active clamp network may be utilized to electrically isolate sea of gates (12) from power rail (18, 20). Substrate (10) includes a voltage potential. When the voltage potential is equal to or greater than a first predetermined value or the voltage potential is equal to or less than a second predetermined value, either the latchup control isolation network turns off or the active clamp network turns on thereby isolating sea of gates (12) from power rail (18, 20).
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2.发明申请公开(公告)号：US20030147187A1
公开(公告)日：2003-08-07
申请号：US09683970
申请日：2002-03-07
发明人： Steven H. Voldman
IPC分类号： H02H009/00
CPC分类号： G06F17/5045
摘要： A computerized method for designing electrostatic discharge (ESD) protection circuits uses a hierarchical system of parametrized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting the design criteria. Ones of the p-cells are nullgrowablenull such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. This allows for change of circuit topology as well as structure size in an automated fashion. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to autogenerate new ESD circuits and ESD power clamps without additional design work. Interconnects and wiring between the circuit elements are also autogenerated.
摘要翻译： 用于设计静电放电（ESD）保护电路的计算机化方法使用构建到更高级ESD网络中的参数化单元（p-cell）的分层系统。 最低阶p单元将用户定义的参数传递到高阶p单元，以形成满足设计标准的ESD保护电路。 p细胞的一部分是“可生长的”，使得它们可以形成下面的p细胞元件的重复组以适应设计参数。 这允许以自动化的方式改变电路拓扑结构以及结构尺寸。 布局和电路原理图是通过用户通过调整输入参数来改变电路中的元件数量而自动生成的。 电路拓扑自动化允许客户自动生成新的ESD电路和ESD电源钳位，无需额外的设计工作。 电路元件之间的互连和接线也是自动生成的。
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3.发明申请Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity 有权深沟槽埋层阵列和用于噪声隔离和闭锁抗扰度的集成器件结构公开(公告)号：US20020084506A1
公开(公告)日：2002-07-04
申请号：US09752061
申请日：2000-12-29
IPC分类号： H01L029/00 , H01L021/336 , H01L021/331 , H01L021/76
CPC分类号： H01L29/66287 , H01L21/761 , H01L21/8249
摘要： The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.
摘要翻译： 本发明的优选实施例提供了一种掩埋层，其提供数字器件的锁定抗扰性，同时提供为数字和模拟设备提供噪声隔离的隔离结构。 优选实施例的掩埋层形成为位于晶体管内的子集电极区域内或下方。 此外，在优选实施例中，子集电极通过在子集电极的边缘处形成的深隔离沟槽与晶体管区域外的掩埋层隔离。 此外，深度隔离沟槽的阵列提供了在需要的器件之间增加的隔离。 因此，本发明的优选实施例提供了一种集成电路结构和方法，其提供改善的闭锁抑制，同时还提供改善的噪声容限。
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4.发明申请Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications 失效碳调制击穿电压SiGe晶体管用于低电压触发ESD应用公开(公告)号：US20030173580A1
公开(公告)日：2003-09-18
申请号：US10063025
申请日：2002-03-13
IPC分类号： H01L031/0328 , H01L031/0336 , H01L031/072 , H01L031/109
CPC分类号： H01L29/0821 , H01L27/0259 , H01L29/1608 , H01L29/7378
摘要： Selectively implanting carbon in a transistor lowers the collector-to-emitter breakdown (BVCEO) of the transistor. This transistor, with the lowered BVCEO, is then used as a nulltriggernull device in an Electrostatic Discharge (ESD) power clamp comprising a first low breakdown trigger device and a second high breakdown clamp device. ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration.
摘要翻译： 在晶体管中选择性地注入碳以降低晶体管的集电极到发射极击穿（BVCEO）。 具有降低的BVCEO的该晶体管然后用作包括第一低击穿触发器件和第二高击穿钳位装置的静电放电（ESD）功率钳中的“触发器”。 ESD功率钳位采用共同收集器达林顿配置中的外延基本伪晶体硅锗异质结晶体管构建。
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公开(公告)号：US20030168701A1
公开(公告)日：2003-09-11
申请号：US09683985
申请日：2002-03-08
发明人： Steven H. Voldman
IPC分类号： H01L023/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.
摘要翻译： 具有低于0.1pF的电容和至少500V的击穿电压的二极管。 二极管具有第一导电类型的阳极和布置在阳极下方的第二导电类型的阴极。 阴极和阳极中的至少一个具有多个垂直邻接的扩散区域。 阴极和阳极设置在相邻隔离区之间并由其限定。
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6.发明申请公开(公告)号：US20040135141A1
公开(公告)日：2004-07-15
申请号：US10248329
申请日：2003-01-09
IPC分类号： H01L029/40
CPC分类号： H01L27/0255 , H01L27/0814 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. A control network can be used to control the biasing when the semiconductor devices are used in a series configuration.
摘要翻译： 一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。 半导体器件优选为二极管结型。 当半导体器件以串联配置使用时，可以使用控制网络来控制偏置。
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7.发明申请METHOD AND STRUCTURE FOR FORMING PRECISION MIM FUSIBLE CIRCUIT ELEMENTS USING FUSES AND ANTIFUSES 审中-公开使用熔丝和抗菌剂形成精密MIM可熔电路元件的方法和结构公开(公告)号：US20040115875A1
公开(公告)日：2004-06-17
申请号：US10707449
申请日：2003-12-15
IPC分类号： H01L021/8238
CPC分类号： H01L23/5252 , H01L23/5223 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element. A capacitor is used in an illustrative example.
摘要翻译： 本发明描述了一种用于制造精密电路元件的装置和方法。 特别地，电路元件被制造为集成电路组件的一部分。 电路元件的处理使得提供与期望值接近的额定电路元件值。 附加的微调电路元件通过链路连接到标称电路元件。 链接是可熔链接或反熔丝。 通过选择性地吹入可熔连接件或熔合反熔丝，对微调电路元件进行加法或减法以个性化标称电路元件的值。 在说明性示例中使用电容器。
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8.发明申请Semiconductor device and method having multiple subcollectors formed on a common wafer 失效具有形成在公共晶片上的多个子集电极的半导体器件和方法公开(公告)号：US20030094673A1
公开(公告)日：2003-05-22
申请号：US09991142
申请日：2001-11-16
IPC分类号： H01L027/082
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/0821
摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.
摘要翻译： 提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。 子集电极可以使用不同的剂量或不同的材料种植体来提供，导致在共同晶片上具有不同最佳单位电流增益截止频率（fT）和击穿电压（BVCEO和BVCBO）的器件。
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公开(公告)号：US20020130392A1
公开(公告)日：2002-09-19
申请号：US09811979
申请日：2001-03-19
IPC分类号： H01L031/117
CPC分类号： H01L29/66242 , H01L29/7304 , H01L29/7378
摘要： A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate; a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the intrinsic base region forming an internal resistor; an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region, the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.
摘要翻译： 公开了一种双极晶体管。 双极晶体管包括：硅衬底; 在半导体衬底中形成的集电体; 形成在集电极上的基极，所述基极具有本征基极区域和非本征基极区域，所述本征基极区域形成内部电阻器; 在本征基区上形成的发射极; 以及形成在外部基极区域和集电极之间的介电层，外部基极区域，电介质层和集电体形成内部电容器。 晶体管的基极可以是硅 - 锗。
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公开(公告)号：US20020056882A1
公开(公告)日：2002-05-16
申请号：US10041509
申请日：2002-01-10
IPC分类号： H01L031/113 , H01L031/062 , H01L029/94 , H01L031/119 , H01L029/76
CPC分类号： H01L29/66659 , H01L27/0266 , H01L27/0288 , H01L29/1083 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An asymmetrical ESD protection device and a method of production thereof are provided. A source region and a drain region are formed in a substrate. A gate is formed over the substrate between the drain and source regions. A compensating implant is formed under the source region. The compensating may either be an additional implant or an existing BR resistor well. The compensating implant extends deeper into the substrate than the drain region.
摘要翻译： 提供了一种不对称的ESD保护装置及其制造方法。 源极区域和漏极区域形成在衬底中。 在漏极和源极区之间的衬底上形成栅极。 在源区下方形成补偿植入物。 补偿可以是额外的植入物或现有的BR电阻阱。 补偿注入比漏极区域更深地延伸到衬底中。
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