公开(公告)号：US20180005826A1

公开(公告)日：2018-01-04

申请号：US15198570

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey P. JACOB ,  Jody FRONHEISER ,  Bruce DORIS ,  Huiming BU

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0638 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66795

Abstract: A method of preventing corner rounding for an alternate channel FINFET formed in trenches and the resulting devices are provided. Embodiments include providing a Si substrate; forming a trench in the Si substrate; forming a Si based layer with a flat upper surface in the trench; and forming a SiGe layer over the Si based layer.

公开(公告)号：US20140264595A1

公开(公告)日：2014-09-18

申请号：US13828283

申请日：2013-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Tenko YAMASHITA ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7855

Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.

Abstract translation: 各种实施例在半导体晶片上形成应变和松弛的硅和锗锗翅片。 在一个实施例中，形成半导体晶片。 半导体晶片包括衬底，电介质层和应变硅锗（SiGe）层。 应变SiGe层的至少一个区域被转化为松弛的SiGe区域。 至少一个应变SiGe鳍由应变SiGe层的第一应变SiGe区形成。 从弛豫SiGe区域的第一部分形成至少一个松弛的SiGe鳍。 在应变SiGe层的第二应变SiGe区域外延生长弛豫硅。 应变硅在弛豫SiGe区域的第二部分外延生长。 从松散的硅形成至少一个松散的硅散热片。 从应变硅形成至少一个应变硅翅片。

公开(公告)号：US20160190303A1

公开(公告)日：2016-06-30

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Hong HE ,  Bruce DORIS

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 制造结构稳定的绝缘体上的FinFET的方法使用氮化硅衬垫来防止在SiGe鳍的基底处的去稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。

公开(公告)号：US20140264602A1

公开(公告)日：2014-09-18

申请号：US14031118

申请日：2013-09-19

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. BASKER ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Tenko YAMASHITA ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7855

Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.

公开(公告)号：US20160013206A1

公开(公告)日：2016-01-14

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract translation: 一种集成电路，包括：UTBOX层; 第一个电池，包括：FDSOI晶体管; 分离晶体管的第一STI; 位于一个晶体管下方并位于UTBOX层之下的第一接地平面; 第一口井 第二个电池，包括：FDSOI晶体管; 分离晶体管的第二STI; 位于一个晶体管下方并位于UTBOX层之下的第二接地平面; 第二口井 分离细胞的第三STI，到达第一和第二孔的底部; 连续地在第一和第二阱下方延伸的深阱，具有在第三STI下面的部分，其掺杂密度比第一和第二STI下面的深井的掺杂密度高至少50％。

公开(公告)号：US20160013205A1

公开(公告)日：2016-01-14

申请号：US14771025

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract translation: 一种集成电路，包括：第一单元，包括：FDSOI晶体管; 位于晶体管下方的UTBOX层; 第一阱位于绝缘体层之下并位于晶体管下方，第一阱具有第一类掺杂; 具有第二类型掺杂的第一接地平面，位于所述晶体管中的一个之下且在所述绝缘体层和所述第一阱之间; 分离晶体管并与绝缘体层交叉的第一STI; 第一导电元件，其形成位于第一STI之下的第一阱和第一接地平面之间的电连接; 包括第二井的第二池; 分离所述电池的第二STI，穿过所述绝缘体层并到达所述第一和第二阱的底部。

公开(公告)号：US20140145254A1

公开(公告)日：2014-05-29

申请号：US14168208

申请日：2014-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Ghavam G. SHAHIDI

IPC: H01L27/06

CPC classification number: H01L21/84 ,  H01L21/32053 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41783

Abstract: An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.

Abstract translation: 电路支撑衬底包括晶体管和电容器。 晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。 栅堆叠包括金属层和第一高k电介质层。 栅极间隔物位于栅极叠层的侧壁上。 第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。 第一硅化物区域位于第一源极/漏极区域上。 第二硅化物区域位于第二源极/漏极区域上。 电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。 第二高k电介质层位于硅化物区域上。 第二端子包括位于第二高k电介质层上的金属层。

公开(公告)号：US20140141575A1

公开(公告)日：2014-05-22

申请号：US14164310

申请日：2014-01-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Ghavam G. SHAHIDI

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/32053 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41783

Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.

Abstract translation: 隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。 在晶体管区域中的第一半导体层上形成虚拟栅极结构。 在第一半导体层上形成第二半导体层。 第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。 第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。 在形成电介质层之后，去除伪栅极结构形成第一腔。 位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。 在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。