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公开(公告)号：US20180060266A1
公开(公告)日：2018-03-01
申请号：US15251097
申请日：2016-08-30
CPC分类号： G06F13/4081 , G06F13/4022 , G06F13/4282
摘要： A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.
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公开(公告)号：US20170154000A1
公开(公告)日：2017-06-01
申请号：US14955805
申请日：2015-12-01
CPC分类号： G06F13/4022 , G06F13/1678 , G06F13/385 , G06F13/4221
摘要： The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each adapter and controls an initial allocation of lanes to each detected adapter for maximizing adapter functionality. After the initial allocation and in response to performance evaluation, the module dynamically switches lanes from the among the adapters, including allocation of available lane, upshifting lane allocation to one or more adapters, and/or downshifting lane allocation to one or more adapters.
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公开(公告)号：US10371717B2
公开(公告)日：2019-08-06
申请号：US15671738
申请日：2017-08-08
IPC分类号： G01R1/067 , G01R1/073 , G01R31/26 , H01L21/66 , H01L23/00 , H01L23/48 , H01L25/065 , G01R31/3185
摘要： Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
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公开(公告)号：US10102074B2
公开(公告)日：2018-10-16
申请号：US14955766
申请日：2015-12-01
摘要： The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter.
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公开(公告)号：US09726691B2
公开(公告)日：2017-08-08
申请号：US14148779
申请日：2014-01-07
IPC分类号： H01L21/66 , G01R31/26 , G01R1/067 , H01L23/00 , G01R1/073 , G01R31/3185 , H01L25/065 , H01L23/48
CPC分类号： G01R1/067 , G01R1/06738 , G01R1/07378 , G01R31/318513 , H01L22/14 , H01L22/30 , H01L22/32 , H01L22/34 , H01L23/481 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L2224/13014 , H01L2224/13016 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/14 , H01L2924/15311 , H01L2924/2064 , H01L2924/20641
摘要： The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.
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公开(公告)号：US20170177179A1
公开(公告)日：2017-06-22
申请号：US15076885
申请日：2016-03-22
IPC分类号： G06F3/0483 , G06F3/0484 , G06F17/28
CPC分类号： G06F3/0483 , G06F3/04842 , G06F17/2235 , G06F17/241
摘要： Provided are techniques for capturing and displaying context information associated with a displayed document, comprising identifying a first plurality of words within a displayed document; applying natural language processing (NPL) to text in proximity to the first plurality of words in the document to identify a first context sensitive usage corresponding to the first plurality of words; storing a reference to the first plurality of words in conjunction with the first context sensitive usage; and in response to a user selection of the first plurality of words, displaying the first context sensitive usage in conjunction with the first plurality of words.
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公开(公告)号：US20170177178A1
公开(公告)日：2017-06-22
申请号：US14970760
申请日：2015-12-16
IPC分类号： G06F3/0483 , G06F17/28
CPC分类号： G06F3/0483 , G06F3/04842 , G06F17/2235 , G06F17/241
摘要： Provided are techniques for capturing and displaying context information associated with a displayed document, comprising identifying a first plurality of words within a displayed document; applying natural language processing (NPL) to text in proximity to the first plurality of words in the document to identify a first context sensitive usage corresponding to the first plurality of words; storing a reference to the first plurality of words in conjunction with the first context sensitive usage; and in response to a user selection of the first plurality of words, displaying the first context sensitive usage in conjunction with the first plurality of words.
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公开(公告)号：US20150192633A1
公开(公告)日：2015-07-09
申请号：US14148779
申请日：2014-01-07
IPC分类号： G01R31/26 , G01R1/067 , H01L23/00 , H01L21/66 , H01L21/768
CPC分类号： G01R1/067 , G01R1/06738 , G01R1/07378 , G01R31/318513 , H01L22/14 , H01L22/30 , H01L22/32 , H01L22/34 , H01L23/481 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L2224/13014 , H01L2224/13016 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/14 , H01L2924/15311 , H01L2924/2064 , H01L2924/20641
摘要： The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.
摘要翻译： 本发明的实施例涉及半导体器件制造，更具体地涉及直接测试具有微焊料连接的半导体晶片的结构和方法。 根据本发明的一个实施例，公开了一种形成与通过（TSV）连接的通过基板的微焊料连接图案的方法，其可以通过电探测直接测试，而不使用测试插入件。 根据另一个实施例，公开了一种测试微焊料连接图案的方法。 根据另一个实施例，公开了一种新颖的电探针尖端结构，其具有与微焊料连接图案相同的间距的接触。
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公开(公告)号：US11193953B2
公开(公告)日：2021-12-07
申请号：US16409277
申请日：2019-05-10
IPC分类号： G01R1/067 , H01L23/00 , H01L25/065 , G01R1/073 , G01R31/3185 , H01L21/66 , G01R31/26 , H01L23/48
摘要： Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
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公开(公告)号：US20190265273A1
公开(公告)日：2019-08-29
申请号：US16409277
申请日：2019-05-10
IPC分类号： G01R1/067 , H01L25/065 , H01L23/00 , G01R1/073 , G01R31/3185
摘要： Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
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