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公开(公告)号:US20040224438A1
公开(公告)日:2004-11-11
申请号:US10863530
申请日:2004-06-07
IPC分类号: H01L021/44 , H01L021/48 , H01L021/50
CPC分类号: H01L23/492 , H01L23/3107 , H01L23/3114 , H01L23/544 , H01L24/81 , H01L24/83 , H01L2223/54486 , H01L2224/1147 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/73153 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/01004 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
摘要翻译: 芯片级封装具有半导体MOSFET管芯,其具有覆盖有感光性液体环氧树脂层的顶部电极表面,该层被光刻图案化以暴露电极表面的部分并且用作钝化层和作为焊接掩模。 然后在钝化层上形成可焊接接触层。 单个管芯的排水侧面向下安装在金属夹子或罐中,其中漏电极设置为与罐底部延伸的凸缘共面。
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公开(公告)号:US20040038509A1
公开(公告)日:2004-02-26
申请号:US10634453
申请日:2003-08-05
IPC分类号: H01L021/44
CPC分类号: H01L23/492 , H01L23/3107 , H01L23/3114 , H01L23/544 , H01L24/81 , H01L24/83 , H01L2223/54486 , H01L2224/1147 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/73153 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/01004 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
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公开(公告)号:US20040026796A1
公开(公告)日:2004-02-12
申请号:US10634447
申请日:2003-08-05
IPC分类号: H01L023/48 , H01L023/52 , H01L029/40
CPC分类号: H01L23/492 , H01L23/3107 , H01L23/3114 , H01L23/544 , H01L24/81 , H01L24/83 , H01L2223/54486 , H01L2224/1147 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/73153 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/01004 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.
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