利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

79 条记录 (耗时 0.021 秒)

    Methodology for image fidelity verification
    1.
    发明授权
    Methodology for image fidelity verification 有权
    图像保真度验证方法

    公开(公告)号：US07860701B2

    公开(公告)日：2010-12-28

    申请号：US11942309

    申请日：2007-11-19

    申请人： Ioana Graur ,  Kafai Lai ,  Rama N. Singh

    发明人： Ioana Graur ,  Kafai Lai ,  Rama N. Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

    摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。

    Methodology for image fidelity verification
    2.
    发明授权
    Methodology for image fidelity verification 有权
    图像保真度验证方法

    公开(公告)号：US07305334B2

    公开(公告)日：2007-12-04

    申请号：US10908724

    申请日：2005-05-24

    申请人： Ioana Graur ,  Kafai Lai ,  Rama N. Singh

    发明人： Ioana Graur ,  Kafai Lai ,  Rama N. Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

    摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。

    METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
    3.
    发明申请
    METHODOLOGY FOR IMAGE FIDELITY VERIFICATION 有权
    用于图像清晰度验证的方法

    公开(公告)号：US20060282246A1

    公开(公告)日：2006-12-14

    申请号：US10908724

    申请日：2005-05-24

    申请人： Ioana Graur ,  Kafai Lai ,  Rama Singh

    发明人： Ioana Graur ,  Kafai Lai ,  Rama Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

    摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。

    METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
    4.
    发明申请
    METHODOLOGY FOR IMAGE FIDELITY VERIFICATION 有权
    图像清晰度验证方法

    公开(公告)号：US20080071512A1

    公开(公告)日：2008-03-20

    申请号：US11942309

    申请日：2007-11-19

    申请人： Ioana Graur ,  Kafai Lai ,  Rama Singh

    发明人： Ioana Graur ,  Kafai Lai ,  Rama Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

    摘要翻译： 一种用于预测光刻印刷在晶片上的集成电路片段的功能性的方法。 最初提供了集成电路的二维设计，包括具有临界宽度的集成电路段，并且模拟了临界宽度集成电路段的二维打印图像。 该方法然后包括确定设计的关键宽度集成电路段的周长或区域与模拟的打印临界宽度集成电路段的比率，以及基于周边或区域的比率来预测打印之后的临界宽度集成电路段的功能。

    Analyzing A Patterning Process Using A Model Of Yield
    5.
    发明申请
    Analyzing A Patterning Process Using A Model Of Yield 失效
    使用产量模型分析模式化过程

    公开(公告)号：US20130185046A1

    公开(公告)日：2013-07-18

    申请号：US13613061

    申请日：2012-09-13

    申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

    摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

    摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

    Analyzing a patterning process using a model of yield
    6.
    发明授权
    Analyzing a patterning process using a model of yield 失效
    使用产量模型分析图案化过程

    公开(公告)号：US08682634B2

    公开(公告)日：2014-03-25

    申请号：US13613061

    申请日：2012-09-13

    申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

    IPC分类号： G06F17/50 ,  G06G7/62

    CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

    摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

    摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

    Directed self-assembly of block copolymers using segmented prepatterns
    9.
    发明授权
    Directed self-assembly of block copolymers using segmented prepatterns 有权
    使用分段预制图的嵌段共聚物的定向自组装

    公开(公告)号：US08398868B2

    公开(公告)日：2013-03-19

    申请号：US12468391

    申请日：2009-05-19

    申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

    发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders

    IPC分类号： B44C1/22 ,  H01L21/302 ,  H01L21/312

    CPC分类号： B81C1/00031 ,  B81C1/00404 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/31144

    摘要： An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

    摘要翻译： 例如使用光刻法形成衬底中的开口，其中开口具有侧壁，其横截面由轮廓和凸形的部分给出。 例如，开口的横截面可以由重叠的圆形区域给出。 侧壁在各个点处相邻，在那里它们限定突起。 将包含嵌段共聚物的聚合物层施加在开口和基底上，并允许自组装。 在开口中形成离散的，分离的畴，其被去除以形成孔，其可以转移到下面的基底中。 这些区域及其对应的孔的位置通过侧壁及其相关联的突起被引导到预定位置。 分离这些孔的距离可以大于或小于如果嵌段共聚物（和任何添加剂）在没有任何侧壁的情况下自组装就会发生。

    Method for optimizing source and mask to control line width roughness and image log slope
    10.
    发明授权
    Method for optimizing source and mask to control line width roughness and image log slope 有权
    优化源和掩码以控制线宽粗糙度和图像对数斜率的方法

    公开(公告)号：US08372565B2

    公开(公告)日：2013-02-12

    申请号：US12872312

    申请日：2010-08-31

    申请人： Kehan Tian ,  Alan E. Rosenbluth ,  David O. Melville ,  Jaione Tirapu Azpiroz ,  Saeed Bagheri ,  Kafai Lai

    发明人： Kehan Tian ,  Alan E. Rosenbluth ,  David O. Melville ,  Jaione Tirapu Azpiroz ,  Saeed Bagheri ,  Kafai Lai

    IPC分类号： G03F9/00

    CPC分类号： G03F1/70 ,  G03F7/70433

    摘要： A method for illuminating a mask with a source to project a desired image pattern through a lithographic system onto a photoactive material including: defining a representation of the mask; obtaining a fractional resist shot noise (FRSN) parameter; determining a first relationship between a first set of optical intensity values and an edge roughness metric based on the FRSN parameter; determining a second relationship between a second set of optical intensity values and a lithographic performance metric; imposing a set of metric constraints based on one of the first and second relationships; setting up an objective function of optimization based on the remaining of the two relationships; determining optimum constrained values of the representation of the mask based on the set of metric constraints and the objective function; and outputting these values.

    摘要翻译： 一种用源照射掩模的方法，用于通过光刻系统将期望的图像图案投影到光活性材料上，包括：限定掩模的表示; 获得分数抗蚀散射噪声（FRSN）参数; 基于所述FRSN参数确定第一组光强度值与边缘粗糙度度量之间的第一关系; 确定第二组光强度值和光刻性能度量之间的第二关系; 基于所述第一和第二关系之一施加一组度量约束; 基于剩余的两个关系建立优化的目标函数; 基于所述度量约束和所述目标函数的集合来确定所述掩码的表示的最佳约束值; 并输出这些值。