公开(公告)号：US08536673B2

公开(公告)日：2013-09-17

申请号：US13092578

申请日：2011-04-22

Applicant: Fumiyasu Utsunomiya ,  Taro Yamasaki ,  Isamu Fujii

Inventor： Fumiyasu Utsunomiya ,  Taro Yamasaki ,  Isamu Fujii

IPC: H01L27/146 ,  H01L31/062

CPC classification number: G01S7/497 ,  H03F3/082

Abstract: Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage. The control circuit outputs a control state output signal, which is a GND terminal voltage when a delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is less than a desired delay amount, and is the drain voltage of the NMOS transistor when the delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is the desired delay amount or more. The light receiving circuit outputs the control state output signal as an output signal.

Abstract translation: 提供了一种用于检测光量变化的光接收电路，其中后级的输入电路紧凑且便宜并且电流消耗低。 光接收电路包括：光电转换元件，用于提供对应于入射光量的电流; 包括提供有来自光电转换元件的电流的漏极的N沟道MOS晶体管; 以及控制电路，用于经由低通滤波器控制NMOS晶体管的栅极电压，使得N沟道MOS晶体管的漏极电压成为期望的电压。 当通过低通滤波器执行的NMOS晶体管的栅极电压的延迟控制量小于期望的延迟量时，控制电路输出作为GND端子电压的控制状态输出信号，并且是漏极电压 当通过低通滤波器执行的NMOS晶体管的栅极电压的延迟控制量是期望的延迟量或更大时，NMOS晶体管。 光接收电路输出控制状态输出信号作为输出信号。

公开(公告)号：US06518835B2

公开(公告)日：2003-02-11

申请号：US10142897

申请日：2002-05-13

Applicant: Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

Inventor： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC: H01L2500

CPC classification number: H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract translation: 一种半导体集成电路器件，包括：第一互连沟道，包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层;第二互连沟道，包括多个第三层金属互连层， 第二方向垂直于第一方向;内部电源电路，其接收从外部端子提供的源极电压并产生与源极电压不同的电压，并且设置有稳定电容器，形成大部分稳定化电容器 在第二和第三层金属互连线彼此相交的区域中。

公开(公告)号：US20100294918A1

公开(公告)日：2010-11-25

申请号：US12800688

申请日：2010-05-20

Applicant: Isamu Fujii

Inventor： Isamu Fujii

IPC: H03F3/08

CPC classification number: H04N5/35527 ,  G01J1/44 ,  G01J2001/446

Abstract: An electric charge storage method is used in which a photoelectric current generated in a photodiode is stored for a predetermined time period and the stored electric charge is amplified by an amplifier to obtain an output. Further, the storage time period is switched so that an output from the circuit has a characteristic of a piecewise linear approximation of a logarithm of an illuminance, permitting a sufficient resolution even in darkness.

Abstract translation: 使用电荷存储方法，其中在光电二极管中产生的光电流存储预定时间段，并且存储的电荷由放大器放大以获得输出。 此外，切换存储时间段，使得来自电路的输出具有对照度的对数的分段线性近似的特性，即使在黑暗中也允许足够的分辨率。

公开(公告)号：US06707139B2

公开(公告)日：2004-03-16

申请号：US09928497

申请日：2001-08-14

Applicant: Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

Inventor： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC: H01L2348

CPC classification number: H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract translation: 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

公开(公告)号：US07414874B2

公开(公告)日：2008-08-19

申请号：US11588328

申请日：2006-10-27

Applicant: Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

Inventor： Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

IPC: G11C5/02

CPC classification number: H01L27/105 ,  G11C5/025 ,  G11C11/4097

Abstract: Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Abstract translation: 公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。 电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。 第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。 第二区域设置有沿第二方向排列的多个第三电路。

公开(公告)号：US20070096156A1

公开(公告)日：2007-05-03

申请号：US11588328

申请日：2006-10-27

Applicant: Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

Inventor： Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

IPC: H01L27/10

CPC classification number: H01L27/105 ,  G11C5/025 ,  G11C11/4097

Abstract: Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Abstract translation: 公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。 电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。 第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。 第二区域设置有沿第二方向排列的多个第三电路。

公开(公告)号：US08748790B2

公开(公告)日：2014-06-10

申请号：US13069831

申请日：2011-03-23

Applicant: Fumiyasu Utsunomiya ,  Taro Yamasaki ,  Isamu Fujii

Inventor： Fumiyasu Utsunomiya ,  Taro Yamasaki ,  Isamu Fujii

IPC: H01L27/00 ,  H01L31/00 ,  H04N7/18 ,  G03B17/00 ,  H01L27/088

CPC classification number: H03K17/941 ,  H03K17/9627 ,  H03K2217/94106 ,  H03K2217/96058

Abstract: Provided is a proximity sensor using a photosensor, which is easy to use and reduced in power consumption. In the proximity sensor, a first photosensor is used to detect a change in amount of ambient light entering the first photosensor, which is caused when a finger is coming close thereto, and a detection signal is output based on a result of the detection. The photosensor includes, for example, one or a plurality of PN junction elements connected in parallel.

Abstract translation: 提供了一种使用光电传感器的接近传感器，其易于使用并降低功耗。 在接近传感器中，使用第一光电传感器来检测当手指靠近其时引起的进入第一光传感器的环境光的变化，并且基于检测结果输出检测信号。 光传感器包括例如并联连接的一个或多个PN结元件。

公开(公告)号：US20100259570A1

公开(公告)日：2010-10-14

申请号：US12822511

申请日：2010-06-24

Applicant: Toshihiko Omi ,  Isamu Fujii ,  Satoshi Machida ,  Toshiyuki Uchida

Inventor： Toshihiko Omi ,  Isamu Fujii ,  Satoshi Machida ,  Toshiyuki Uchida

IPC: G09G5/10 ,  G01J1/42

CPC classification number: H01L27/14645 ,  G01J1/02 ,  G01J1/0488 ,  G01J1/18 ,  G01J1/4228 ,  G01J1/44 ,  H01L27/14621 ,  H04N5/37457

Abstract: Provided is a photodetection device which is small in size and has excellent sensitivity. A photodetection device puts cathode terminals of photodiodes having different spectral characteristics into an open end state, and detects light intensity of a desired wavelength region according to a difference in electric charges that have been stored in those photodiodes in a given period of time. The photodiodes employ a system of storing electric charges, and hence even if a photocurrent is small, the photocurrent may be stored to obtain the electric charges required for detection, and the downsizing and high detection performance of a semiconductor device that forms the photodiodes may be achieved. Further, a wide dynamic range may be realized with an electric charge storage time being variable according to the light intensity, to intermittently drive an element required for difference detection at the time of difference detection so as to suppress electric power consumption, or to average the output so as to reduce flicker.

Abstract translation: 提供了一种尺寸小且灵敏度高的光检测装置。 光检测装置将具有不同光谱特性的光电二极管的阴极端子设置为开放状态，并且根据在给定时间段内存储在那些光电二极管中的电荷的差异来检测期望波长区域的光强度。 光电二极管使用存储电荷的系统，因此即使光电流小，也可以存储光电流以获得检测所需的电荷，并且形成光电二极管的半导体器件的小型化和高检测性能可以是 实现了 此外，可以通过根据光强度可变的电荷存储时间来实现宽的动态范围，以间歇地驱动差分检测时的差分检测所需要的元件以抑制电力消耗，或者使 输出以减少闪烁。

公开(公告)号：US06411160B1

公开(公告)日：2002-06-25

申请号：US09376470

申请日：1999-08-18

Applicant: Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

Inventor： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC: H01L2500

CPC classification number: H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract translation: 在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层 内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于 第二和第三层金属互连线彼此相交的区域。

公开(公告)号：US06408195B1

公开(公告)日：2002-06-18

申请号：US09202915

申请日：2000-02-14

Applicant: Yuji Hishiki ,  Isamu Fujii ,  Shinichi Idomukai

Inventor： Yuji Hishiki ,  Isamu Fujii ,  Shinichi Idomukai

IPC: G06F1300

CPC classification number: H04L25/05 ,  H04W52/029 ,  Y02D70/00

Abstract: An IC for communication includes a single oscillating circuit, which is capable of flexibly dealing with the change of data rate or data processing load, and is produced at a low cost and consumes low electric power. In the IC for communication, a frequency multiplying circuit(61) is inserted between the output of an oscillating circuit(1) and a micro-controller circuit(69), or a frequency dividing circuit(2) is inserted between the oscillating circuit(1) and a data receiving circuit(3). A receiving address is stored in a dual port RAM(16). Further, by controlling a receiving frequency of synchronous codes, battery saving efficiency is increased.

Abstract translation: 用于通信的IC包括单个振荡电路，其能够灵活地处理数据速率或数据处理负载的变化，并且以低成本生产并且消耗低功率。 在用于通信的IC中，在振荡电路（1）的输出端和微控制器电路（69）之间插入一个倍频电路（61），或者分频电路（2）插在振荡电路 1）和数据接收电路（3）。 接收地址存储在双端口RAM（16）中。 此外，通过控制同步码的接收频率，提高了电池节省效率。