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公开(公告)号：US20150177801A1
公开(公告)日：2015-06-25
申请号：US14140219
申请日：2013-12-24
申请人： Ivan Herrera Mejia , Zeev Offen
发明人： Ivan Herrera Mejia , Zeev Offen
CPC分类号： G06F1/26 , G06F1/24 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/24 , G06F9/4418 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.
摘要翻译： 包括相关联的系统，方法和装置的实施例，其提供了芯片上的系统（SoC）的北复合体和南复合体之间的接口。 在实施例中，北复合体可以包括输入信号要求中的微控制器。 上电控制块可以与微控制器耦合，并且上电控制块可以被配置为从南复合体的组件接收控制信号，并且至少部分地基于输入信号来改变控制信号 要求微控制器。
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2.发明申请SIMULATING LOSS OF LOGIC POWER STATE DUE TO PROCESSOR POWER CONSERVATION STATE 有权模拟处理器功率保存状态下的逻辑功率状态的损失公开(公告)号：US20100169065A1
公开(公告)日：2010-07-01
申请号：US12346956
申请日：2008-12-31
IPC分类号： G06F17/00
CPC分类号： G06F1/30
摘要： In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.
摘要翻译： 通常，在一个方面，本公开描述了仅包括集成电路（IC）的逻辑状态的子集的随机化列表的创建。 该子集由信号选择，以便定义可针对特定事件随机化的逻辑状态。 随机化列表是在模拟期间随机化其中定义的逻辑状态以模拟在IC的操作期间发生的特定事件。 例如，随机化列表可以包括在从掉电状态（例如，深度掉电，C6）退出时可以随机化的那些信号。 可以随机化的信号可以通过排除不能被随机化的信号（在C6模式下仍然接收功率）来定义。 随机化并退出C6模式后，可以确认IC寄存器的内容。
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3.发明授权Method and apparatus for implementing a secure boot using multiple firmware sources 有权用于使用多个固件源实现安全引导的方法和装置公开(公告)号：US09384351B2
公开(公告)日：2016-07-05
申请号：US13839892
申请日：2013-03-15
IPC分类号： G06F21/00 , G06F21/57 , H01L27/112
CPC分类号： G06F21/575 , G06F21/572 , H01L27/11206
摘要： Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.
摘要翻译： 描述使用多个固件源实现安全引导的技术。 可以配置处理装置的一个或多个保险丝。 基于这样的配置，可以生成一个或多个键。 基于各种保险丝的配置，可以启动固件设备的操作。 使用生成的密钥，可以访问固件设备的受保护部分。
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4.发明申请ADAPTIVE CONTROL LOOP PROTECTION FOR FAST AND ROBUST RECOVERY FROM LOW-POWER STATES IN HIGH SPEED SERIAL I/O APPLICATIONS 有权用于在低功率状态下在高速串行I / O应用中进行快速和可靠的恢复的自适应控制环路保护公开(公告)号：US20140281668A1
公开(公告)日：2014-09-18
申请号：US13831892
申请日：2013-03-15
IPC分类号： G06F11/07
CPC分类号： G06F1/26 , G06F1/00 , G06F1/3253 , G06F11/0706 , G06F11/0754 , G06F11/0793 , Y02D10/151
摘要： Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.
摘要翻译： 描述了与高速串行I / O应用中的低功率状态快速稳健恢复的自适应控制回路保护相关的方法和设备。 在一些实施例中，在第一代理处检测到第一位模式，其指示由第二代理进入低功耗状态的推测输入，并且一个或多个控制回路被冻结。 检测到第二位模式（在进入低功耗状态之后），其指示由第二代理从低功耗状态退出并且一个或多个控制回路被解冻（例如，以特定顺序）。 还要求和/或公开其它实施例。
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5.发明申请METHOD AND APPARATUS FOR IMPLEMENTING A SECURE BOOT USING MULTIPLE FIRMWARE SOURCES 有权使用多个固件来实现安全引导的方法和装置公开(公告)号：US20140281456A1
公开(公告)日：2014-09-18
申请号：US13839892
申请日：2013-03-15
IPC分类号： G06F9/44
CPC分类号： G06F21/575 , G06F21/572 , H01L27/11206
摘要： Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.
摘要翻译： 描述使用多个固件源实现安全引导的技术。 可以配置处理装置的一个或多个保险丝。 基于这样的配置，可以生成一个或多个键。 基于各种保险丝的配置，可以启动固件设备的操作。 使用生成的密钥，可以访问固件设备的受保护部分。
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公开(公告)号：US20140258698A1
公开(公告)日：2014-09-11
申请号：US13791218
申请日：2013-03-08
CPC分类号： G06F1/28 , G06F1/30 , G06F9/4401 , G06F9/4406 , G06F11/00
摘要： An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.
摘要翻译： 诸如SoC的集成电路可以指示关键的电池状态，而不需要在包括主机处理核心的实质部分上供电。 SoC可以包括微控制器，其可以使得临界电池状态数据被存储在静态存储器中，并且显示单元可以从静态存储器检索这样的数据，以在屏幕上显示视觉符号。 SoC的其他部分，例如动态存储器，系统代理，媒体处理器和存储器控制器集线器可以被关闭，而临界电池状态以视觉形式显示在屏幕上。
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7.发明申请PRESET EVALUATION TO IMPROVE INPUT/OUTPUT PERFORMANCE IN HIGH-SPEED SERIAL INTERCONNECTS 有权预测评估提高高速串行互连中的输入/输出性能公开(公告)号：US20140237301A1
公开(公告)日：2014-08-21
申请号：US13767881
申请日：2013-02-15
申请人： Ivan Herrera Mejia , Manuel A. Aguilar Arreola , Shrinivas Venkatraman , Andrea R. Vavra , Pavel Konev
发明人： Ivan Herrera Mejia , Manuel A. Aguilar Arreola , Shrinivas Venkatraman , Andrea R. Vavra , Pavel Konev
IPC分类号： G06F11/30
CPC分类号： G06F13/4282 , G06F9/4411 , G06F13/385 , G06F13/4072 , G06F2213/0026
摘要： Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.
摘要翻译： 描述了利用预设评估来提高高速串行互连中的输入/输出性能的方法和装置。 在一些实施例中，在多个均衡值处评估链路的性能，并且基于为多个均衡值中的每一个确定的多个边缘值的比较来为链路选择多个均衡值中的一个 价值观。 还要求和/或公开其它实施例。
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8.发明授权Simulating loss of logic power state due to processor power conservation state 有权由于处理器功率节省状态，模拟逻辑电源状态的损失公开(公告)号：US08112265B2
公开(公告)日：2012-02-07
申请号：US12346956
申请日：2008-12-31
IPC分类号： G06F17/50
CPC分类号： G06F1/30
摘要： In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.
摘要翻译： 通常，在一个方面，本公开描述了仅包括集成电路（IC）的逻辑状态的子集的随机化列表的创建。 该子集由信号选择，以便定义可针对特定事件随机化的逻辑状态。 随机化列表是在模拟期间随机化其中定义的逻辑状态以模拟在IC的操作期间发生的特定事件。 例如，随机化列表可以包括在从掉电状态（例如，深度掉电，C6）退出时可以随机化的那些信号。 可以随机化的信号可以通过排除不能被随机化的信号（在C6模式下仍然接收功率）来定义。 随机化并退出C6模式后，可以确认IC寄存器的内容。
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