INDICATING CRITICAL BATTERY STATUS IN MOBILE DEVICES
    1.
    发明申请
    INDICATING CRITICAL BATTERY STATUS IN MOBILE DEVICES 有权
    指出移动设备中的关键电池状态

    公开(公告)号:US20140258698A1

    公开(公告)日:2014-09-11

    申请号:US13791218

    申请日:2013-03-08

    IPC分类号: G06F1/28 G06F9/44

    摘要: An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.

    摘要翻译: 诸如SoC的集成电路可以指示关键的电池状态,而不需要在包括主机处理核心的实质部分上供电。 SoC可以包括微控制器,其可以使得临界电池状态数据被存储在静态存储器中,并且显示单元可以从静态存储器检索这样的数据,以在屏幕上显示视觉符号。 SoC的其他部分,例如动态存储器,系统代理,媒体处理器和存储器控制器集线器可以被关闭,而临界电池状态以视觉形式显示在屏幕上。

    Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance
    2.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance 有权
    能量效率和节能的方法,装置和系统,包括动态高速缓存大小和高速缓存操作电压管理,实现最佳功率性能

    公开(公告)号:US08713256B2

    公开(公告)日:2014-04-29

    申请号:US13336977

    申请日:2011-12-23

    IPC分类号: G06F12/00

    摘要: Embodiments described herein vary an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.

    摘要翻译: 本文描述的实施例基于处理器实际使用的缓存的量来改变可用于由处理器使用的高速缓存的数量和提供给高速缓存和处理器的功率量。 例如,功率控制单元(PCU)可以监视最后一级高速缓存(LLC)以识别处理器正在使用的高速缓存的大小或数量来处理数据,并且基于该量来确定启发式。 基于所使用的缓存的监视量和启发式,PCU引起可用于处理器的缓存的量的相应减少或增加,并且相应地降低或增加提供给高速缓存的功率量,以及 到处理器。

    Controlling Operating Voltage Of A Processor
    5.
    发明申请
    Controlling Operating Voltage Of A Processor 有权
    控制处理器的工作电压

    公开(公告)号:US20140258760A1

    公开(公告)日:2014-09-11

    申请号:US13793037

    申请日:2013-03-11

    IPC分类号: G06F1/26

    摘要: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器,该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压,以指示电压 调节器将工作电压增加到临时电压,然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。

    Distributing Power To Heterogeneous Compute Elements Of A Processor
    6.
    发明申请
    Distributing Power To Heterogeneous Compute Elements Of A Processor 审中-公开
    将功率分配给处理器的异构计算元素

    公开(公告)号:US20140082380A1

    公开(公告)日:2014-03-20

    申请号:US13783986

    申请日:2013-03-04

    IPC分类号: G06F1/26

    摘要: In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括处理器,其具有具有第一计算引擎的第一域和具有第二计算引擎的第二域,其中这些域中的每一个可以以独立的电压和频率工作。 可以存在第一逻辑来至少部分地基于第二域的繁忙来更新用于控制第一和第二域之间的功率的动态分配的功率偏置值。 反过来,第二逻辑可以至少部分地基于该功率偏差值来在区域之间动态分配处理器的功率预算的至少一部分。 描述和要求保护其他实施例。