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公开(公告)号：US06362532B1
公开(公告)日：2002-03-26
申请号：US09536965
申请日：2000-03-28
申请人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
发明人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
IPC分类号： H01L2328
CPC分类号： H01L23/3107 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/81 , H01L29/0657 , H01L2224/11 , H01L2224/1134 , H01L2224/1191 , H01L2224/13 , H01L2224/1308 , H01L2224/13124 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2224/274 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/94 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/03
摘要： A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.
摘要翻译： 一种用于形成半导体器件的方法包括以下步骤：提供其上具有多个焊盘的半导体管芯，其中至少一个接合线与所述焊盘中的一个电连接并提供其中具有空腔的保持器。 将模具放置在空腔中，然后在空腔内形成一层封装以覆盖模具。 随后，将封装的模头从空腔中取出。
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公开(公告)号：US06043564A
公开(公告)日：2000-03-28
申请号：US175807
申请日：1998-10-20
申请人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
发明人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
IPC分类号： H01L21/60 , H01L23/28 , H01L23/31 , H01L23/485 , H01L29/06
CPC分类号： H01L23/3107 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/1134 , H01L2224/1191 , H01L2224/13 , H01L2224/1308 , H01L2224/13124 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2224/274 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/94 , H01L24/45 , H01L24/48 , H01L29/0657 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/181
摘要： A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.
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公开(公告)号：US5824569A
公开(公告)日：1998-10-20
申请号：US611314
申请日：1996-03-05
申请人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
发明人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
CPC分类号： H01L23/3107 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/1134 , H01L2224/1191 , H01L2224/13 , H01L2224/1308 , H01L2224/13124 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2224/274 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/94 , H01L24/45 , H01L24/48 , H01L29/0657 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/181
摘要： A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.
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公开(公告)号：US06326245B1
公开(公告)日：2001-12-04
申请号：US09396439
申请日：1999-09-15
IPC分类号： H01L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译： 形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。 逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。 本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。 本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。
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公开(公告)号：US6093933A
公开(公告)日：2000-07-25
申请号：US39230
申请日：1998-03-16
CPC分类号： G11C29/88 , G11C29/006 , G11C5/063 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
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公开(公告)号：US06797545B2
公开(公告)日：2004-09-28
申请号：US10259510
申请日：2002-09-30
IPC分类号： H10L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译： 形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。 逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。 本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。 本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。
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公开(公告)号：US06531345B2
公开(公告)日：2003-03-11
申请号：US09917695
申请日：2001-07-31
IPC分类号： H01L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译： 形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。 逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。 本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。 本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。
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8.发明申请RANDOM ACCESS MEMORY DEVICE UTILIZING A VERTICALLY ORIENTED SELECT TRANSISTOR 有权使用垂直方向的选择晶体管的随机存取存储器件公开(公告)号：US20100276742A1
公开(公告)日：2010-11-04
申请号：US12834382
申请日：2010-07-12
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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公开(公告)号：US07128551B2
公开(公告)日：2006-10-31
申请号：US10230647
申请日：2002-08-29
IPC分类号： B29C35/08
CPC分类号： G03F7/0037 , B29C37/005 , B29C41/48 , B29C64/40 , B29C73/00 , B29C2035/0827 , B29C2035/0838 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , Y10S430/146
摘要： A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.
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公开(公告)号：US06709795B2
公开(公告)日：2004-03-23
申请号：US10230471
申请日：2002-08-29
IPC分类号： G03F716
CPC分类号： G03F7/0037 , B29C37/005 , B29C41/48 , B29C64/40 , B29C73/00 , B29C2035/0827 , B29C2035/0838 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , Y10S430/146
摘要： A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.
摘要翻译： 一种用于形成包含多个上层的聚合物结构的立体光刻方法和装置，每个层通过在先前层上聚合薄层的液体光聚合物而形成。 在层界面处形成的裂缝由立体光刻法填充，其包括从液体光聚合物提起多层结构，从其中排出多余的液体，使结构倾斜以提供入射辐射束与物体的侧壁之间的锐角入射角， 并向所述缝隙施加辐射以至少使其中的液体光聚合物的表面聚合。 然后可以对该结构进行单独的最终完全固化以使结构完全硬化。 示例性的用途是电子部件等的包装。
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