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1.发明申请RANDOM ACCESS MEMORY DEVICE UTILIZING A VERTICALLY ORIENTED SELECT TRANSISTOR 有权使用垂直方向的选择晶体管的随机存取存储器件公开(公告)号：US20100276742A1
公开(公告)日：2010-11-04
申请号：US12834382
申请日：2010-07-12
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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2.发明授权Random access memory device utilizing a vertically oriented select transistor 有权利用垂直取向的选择晶体管的随机存取存储器件公开(公告)号：US07205598B2
公开(公告)日：2007-04-17
申请号：US10637557
申请日：2003-08-11
IPC分类号： H01L27/108
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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3.发明授权Random access memory device utilizing a vertically oriented select transistor 有权利用垂直取向的选择晶体管的随机存取存储器件公开(公告)号：US08431980B2
公开(公告)日：2013-04-30
申请号：US12834382
申请日：2010-07-12
IPC分类号： H01L27/108
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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4.发明授权Random access memory device utilizing a vertically oriented select transistor 有权利用垂直取向的选择晶体管的随机存取存储器件公开(公告)号：US07777264B2
公开(公告)日：2010-08-17
申请号：US11708616
申请日：2007-02-21
IPC分类号： H01L27/108
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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5.发明授权Method of fabricating a random access memory device utilizing a vertically oriented select transistor 失效使用垂直取向的选择晶体管制造随机存取存储器件的方法公开(公告)号：US06951789B2
公开(公告)日：2005-10-04
申请号：US10878059
申请日：2004-06-29
IPC分类号： G11C11/24 , G11C11/404 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/423 , H01L29/76 , H01L29/78
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 也可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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公开(公告)号：US07123530B2
公开(公告)日：2006-10-17
申请号：US10681161
申请日：2003-10-09
申请人： Thomas W. Voshell
发明人： Thomas W. Voshell
IPC分类号： G11C7/02
CPC分类号： G11C13/0061 , G11C7/06 , G11C11/1673 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2213/79
摘要： Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding to the logic sate of the memory cell.
摘要翻译： 交流电用于检测具有电阻性存储元件的存储单元的逻辑状态。 存储器元件可以是阵列，并且存储器件可以包括用于读取或感测阵列中的每个存储器单元的阵列和外围电路。 外围电路可以包括提供控制信号的时钟/控制电路，该控制信号控制何时检测一行存储器单元，用于接收单元板计数信号的开关电路和由时钟/控制电路提供的位计数信号，单元板 所述开关电路产生第一输出信号和第二输出信号，其中所述第一输出信号和所述第二输出信号中的一个处于电源电压，并且所述第一输出中的另一个输出信号 信号和第二输出信号与每个感测操作交替极性，并且比较电路接收第一输出信号和第二输出信号，并输出与存储器单元的逻辑状态对应的信号。
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公开(公告)号：US06446226B1
公开(公告)日：2002-09-03
申请号：US09749103
申请日：2000-12-26
IPC分类号： G11C2900
CPC分类号： G01R31/318558 , G01R31/31919 , H03K3/78
摘要： A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.
摘要翻译： 描述了用于提供脉冲以测试诸如存储器件的半导体器件的系统。 该系统包括多个电压源，每个电压源通过通过门耦合到输出端。 控制逻辑电路向每个通过门提供控制信号，以使得通过栅极按顺序导通。 由每个电压源产生的电压按顺序耦合到输出端，以在输出端产生一系列脉冲。 每个电压源可以是接收电压控制信号并基于电压控制信号产生电压的可编程数模转换器。
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公开(公告)号：US5276834A
公开(公告)日：1994-01-04
申请号：US621869
申请日：1990-12-04
CPC分类号： G11C29/76 , G06F11/1044
摘要： A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).
摘要翻译： 一种备用存储器装置，其中存储器阵列中的有缺陷的芯片可以用相同结构的备用芯片电子地替代。 首先通过诸如纠错码（ECC），校验和或奇偶校验的适当手段来检测和定位有缺陷的存储器芯片。 构成了在读取缺陷存储器芯片时利用存储器备用芯片来替换有缺陷的芯片的致动器芯片。 该支持者芯片包括具有用于从中央处理单元（CPU）接收数据并将数据路由到备用存储器芯片的数据的地址寄存器的交叉点存储器（CPM）单元。 交叉点存储器（CPM）单元由来自（CPU）的控制输入启动。
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9.发明授权Method and circuit for controlling a field emission display for reducing emission to grid 失效用于控制场发射显示以减少发射到电网的方法和电路公开(公告)号：US06291941B1
公开(公告)日：2001-09-18
申请号：US09261589
申请日：1999-03-03
IPC分类号： G09G310
CPC分类号： H01J3/022 , G09G3/22 , G09G2300/08 , G09G2330/026 , H01J2329/00
摘要： A method and a control circuit for controlling a field emission display to reduce emission to grid during turn on and turn off are provided. In an illustrative embodiment, the control circuit includes a threshold detector that receives an input signal proportional to an anode voltage (VAnode) for the display and produces a high or low output signal dependent on the level of VAnode. An output low corresponding to a high voltage at the display screen enables a gate element of a pass transistor that controls current flow to the grid. Alternately, an output high corresponding to a low voltage at the display screen enables a pull down transistor that controls discharge of the grid to ground. The control circuit can also include a fault detection circuit for detecting a sharp decrease in the anode voltage and discharging the grid. In an alternate embodiment, the control circuit shorts the emitter sites together during turn on and turn off and provides a high source impedance to restrict current flow to any one emitter site. The high source impedance can be permanent or switchable by a relay or switching circuit.
摘要翻译： 提供一种用于控制场致发射显示以在打开和关闭期间减少到格栅的发射的方法和控制电路。 在说明性实施例中，控制电路包括阈值检测器，其接收与用于显示器的阳极电压（VAnode）成比例的输入信号，并且根据VAnode的电平产生高或低输出信号。 与显示屏幕上的高电压相对应的输出低电平使得能够控制电流流向电网的通过晶体管的栅极元件。 或者，对应于显示屏幕处的低电压的输出高电平使得能够控制电网到地的放电的下拉晶体管。 控制电路还可以包括用于检测阳极电压急剧下降并排出电网的故障检测电路。 在替代实施例中，控制电路在导通和断开期间将发射极点一起短路，并提供高的源阻抗以限制电流流向任何一个发射器位置。 高源阻抗可以由继电器或开关电路永久或切换。
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10.发明授权Flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage 失效平板显示器，其中低电压行和列地址信号控制高得多的像素激活电压
公开(公告)号：US5616991A
公开(公告)日：1997-04-01
申请号：US530562
申请日：1995-09-19
CPC分类号： G09G3/006 , G09G3/22 , H01J31/127 , G09G2300/0809 , G09G2310/0248 , G09G2310/0259 , G09G2320/0606 , G09G2320/0626 , G09G2320/066 , G09G3/2011 , G09G3/2014 , H01J2201/319 , Y10S315/07
摘要： This invention is directed to an improvement of a field emission display architecture in which low-voltage row and column address signals control a much higher pixel activation voltage. Instead of using a pair of series-coupled transistors in the emitter node grounding path as in the original architecture (one of which is gated by a column signal and the other of which is gated by a row signal), only a single transistor is utilized in the emitter node grounding path, thus eliminating an intermediate node between the two transistors that was responsible for unwanted emissions under certain operating conditions. In a preferred embodiment of the invention, a current regulating resistor is placed in the grounding path in series with the primary grounding transistor, with the resistor being directly coupled to ground. Additionally, for the preferred embodiment of the invention, the gate of the grounding transistor is coupled via a second field-effect transistor to either a row signal or a column signal. In the case where the gate of the first transistor is coupled to a row signal, the gate of the second transistor is coupled to a column signal. Likewise, where the gate of the first transistor is coupled to a column signal, the gate of the second transistor is coupled to a row signal. Numerous other equivalent circuits are possible, and several examples of such equivalent circuits are depicted in this disclosure.
摘要翻译： 本发明涉及一种场致发射显示结构的改进，其中低电压行和列地址信号控制高得多的像素激活电压。 不像原始架构（其中之一由列信号门控，另一个由行信号门控）在发射极节点接地路径中使用一对串联耦合晶体管，而是仅使用单个晶体管 在发射极节点接地路径中，从而消除了在某些工作条件下负责无用发射的两个晶体管之间的中间节点。 在本发明的优选实施例中，电流调节电阻器被放置在与主接地晶体管串联的接地路径中，电阻器直接耦合到地。 此外，对于本发明的优选实施例，接地晶体管的栅极经由第二场效应晶体管耦合到行信号或列信号。 在第一晶体管的栅极耦合到行信号的情况下，第二晶体管的栅极耦合到列信号。 类似地，在第一晶体管的栅极耦合到列信号的情况下，第二晶体管的栅极耦合到行信号。 许多其他等效电路是可能的，并且在本公开中描述了这些等效电路的几个示例。
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