公开(公告)号：US06466148B1

公开(公告)日：2002-10-15

申请号：US09672608

申请日：2000-09-28

申请人： Jacob Wikner ,  Mark Vesterbacka

发明人： Jacob Wikner ,  Mark Vesterbacka

IPC分类号： H03M166

CPC分类号： H03M1/0678 ,  H03M1/0663 ,  H03M1/0673 ,  H03M1/745

摘要： A D/A converter includes a triangular unit weight array. A decoder transforms digital samples into control signals having a linearly weighted binary representation. These control signal are used for activation/deactivation of entire rows or columns of the triangular unit weight array. Finally, the unit weights are combined into an analog output signal.

摘要翻译： D / A转换器包括三角形单位重量阵列。 解码器将数字样本转换成具有线性加权二进制表示的控制信号。 这些控制信号用于激活/去激活三角形单位重量阵列的整个行或列。 最后，将单位权重组合成模拟输出信号。

公开(公告)号：US06462691B2

公开(公告)日：2002-10-08

申请号：US09861525

申请日：2001-05-22

申请人： Mikael Karlsson Rudberg ,  Mark Vesterbacka ,  Niklas Andersson ,  Jacob Wikner

发明人： Mikael Karlsson Rudberg ,  Mark Vesterbacka ,  Niklas Andersson ,  Jacob Wikner

IPC分类号： H03M166

CPC分类号： H03M7/165 ,  H03M1/0673 ,  H03M1/0863 ,  H03M7/26

摘要： To minimize the number of positions to be altered in a transition from one output data word to the next in a scrambler for scrambling successive, thermometer coded binary input data words comprising N bits into corresponding successive output data words also comprising N bits, the scrambler is adapted, if the number of bits of one binary value has increased from one input data word to the next, to maintain bits of said one binary value in positions in the corresponding output data word where the previous output data word had bits of said one binary value, and to randomize the remaining bits of said one binary value to positions in the corresponding output data word where the previous output data word had bits of the other binary value.

公开(公告)号：US20110248876A1

公开(公告)日：2011-10-13

申请号：US13122824

申请日：2009-10-09

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03M1/36

CPC分类号： H03M1/1023 ,  H03M1/0682 ,  H03M1/1004 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/682 ,  H03M1/765

摘要： A parallel successive-approximation analog-to-digital converter (PSA-ADC, 10) comprises a reference-voltage generation unit and a plurality of sub ADCs, (ADC-1, . . . , ADC-M) arranged for successive-approximation operation in a time-interleaved manner. Each sub ADC (ADC-1, . . . , ADC-M) comprises a reference-voltage selection unit (45, 45′) for selecting a reference voltage generated by the reference-voltage generation unit (35, 35′) based on a digital number XSA stored in a successive-approximation register (SAR, 70) of the sub ADC (ADC-1, . . . , ADC-M) and forwarding the selected reference voltage to a comparator arrangement of the sub ADC (ADC-1, . . . , ADC-M). The reference-voltage selection unit (45, 45′) comprises a ADC-1 first and a second switch layer. The first switch layer comprises a plurality of switch groups, wherein each switch group comprises a plurality of switch devices (120-0, . . . , 120-15), each operatively connected to a unique output terminals (40-0, . . . , 40-n) of the reference-voltage generation unit (35, 35′) with a first terminal and to a common node (125a-d) of the switch group with a second terminal. The second switch layer comprises a switch device (130a, 135a, 140a, 145a) operatively connected between the common node (125a-d) of each switch group and the first output terminal (55a, 55′a) of the reference-voltage selection unit (45, 45′) and a switch device (130b, 135b, 140b, 145b) operatively connected between the common node (125a-d) of each switch group and the second output terminal (55b, 55′b) of the reference-voltage selection unit (45, 45′). A control unit (60, 60′) of each sub ADC is arranged to generate control signals for the switch devices in the reference-voltage selection unit (45, 45′) of the sub ADC (ADC-1, . . . , ADC-M) based on the digital number X SA in the SAR (70) of the sub ADC (ADC-1, . . . , ADC-M).

公开(公告)号：US20090009225A1

公开(公告)日：2009-01-08

申请号：US12193401

申请日：2008-08-18

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.

摘要翻译： 一种用于向集成电路产生时钟信号的时钟信号发生器。 时钟信号发生器包括适于基于参考时钟信号产生多个相互延迟的时钟相位的延迟锁定环路。 延迟锁定环路还适于响应于第一控制信号而选择多个时钟相位中的一个作为延迟锁定环路的输出信号，其中所述输出信号是第一时钟信号。 时钟信号发生器还包括反相器，被配置为产生输出信号的反相;以及多路复用器单元，其被配置为响应于时钟转换信号，将输出信号或反相输出作为第二时钟信号 。

公开(公告)号：US08456347B2

公开(公告)日：2013-06-04

申请号：US13122824

申请日：2009-10-09

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03M1/36

CPC分类号： H03M1/1023 ,  H03M1/0682 ,  H03M1/1004 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/682 ,  H03M1/765

摘要： An analog-to-digital converter including a voltage generation unit and a plurality of sub ADCs, each including a selection unit for selecting a voltage generated by the voltage generation unit based on a number and forwarding the selected voltage to a comparator arrangement. The selection unit includes first and second switch layers. The first switch layer includes a plurality of switch groups, each including a plurality of switch devices, each connected to a unique output terminal of the voltage generation unit with a first terminal and to a common node of the switch group with a second terminal. The second switch layer includes a switch device between the common node of each switch group and the first output terminal of the selection unit and a switch device between the common node and the second output terminal of the selection unit. A control unit generates control signals for the switch devices.

摘要翻译： 一种包括电压产生单元和多个子ADC的模数转换器，每个子ADC包括一个选择单元，用于基于一个数字选择由电压产生单元产生的电压，并将所选择的电压转送到比较器装置。 选择单元包括第一和第二开关层。 第一开关层包括多个开关组，每个开关组包括多个开关装置，每个开关装置与第一端子连接到具有第一端子的电压产生单元的唯一输出端子以及具有第二端子的开关组的公共节点。 第二开关层包括在每个开关组的公共节点和选择单元的第一输出端之间的开关装置和选择单元的公共节点和第二输出端之间的开关装置。 控制单元产生开关装置的控制信号。

公开(公告)号：US07830291B2

公开(公告)日：2010-11-09

申请号：US12279437

申请日：2007-01-18

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03M1/12

CPC分类号： H03M1/186

摘要： An analog-to-digital converter (1). The analog to digital converter (1) comprises a first range-control unit (100) adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter (1). The analog to digital converter further comprises a second range-control unit (200) adapted to generate a second range-control value for controlling a midpoint of the input range. Further, the analog-to-digital converter (1) comprises a reference-level unit (300) operatively connected to the first range-control unit (100) and the second range-control unit (200). The reference-level unit (300) is arranged to generate a plurality of reference levels at least based on the first and the second range-control value. The analog-to-digital converter further comprises a comparison unit (400) operatively connected to the second range-control unit (200) and the reference-level unit (300). The comparison unit (400) is arranged to perform at least one comparison between a difference between an analog input value of the analog-to-digital converter (1) and the second range-control value and individual reference levels of the plurality of reference levels. The comparison unit (400) is further arranged to generate a digital output value of the analog-to-digital converter (1) based on the at least one comparison.

摘要翻译： 一个模拟 - 数字转换器（1）。 模数转换器（1）包括适于产生用于控制模数转换器（1）的输入范围的大小的第一范围控制值的第一范围控制单元（100）。 模数转换器还包括适于产生用于控制输入范围的中点的第二范围控制值的第二范围控制单元（200）。 此外，模数转换器（1）包括可操作地连接到第一范围控制单元（100）和第二范围控制单元（200）的参考级单元（300）。 参考级单元（300）被布置成至少基于第一和第二范围控制值来生成多个参考电平。 模数转换器还包括可操作地连接到第二范围控制单元（200）和参考级单元（300）的比较单元（400）。 比较单元（400）被布置成执行模数转换器（1）的模拟输入值与第二范围控制值之间的差异与多个参考电平的单独参考电平之间的至少一个比较 。 比较单元（400）还被布置成基于至少一个比较来产生模数转换器（1）的数字输出值。

公开(公告)号：US07595673B2

公开(公告)日：2009-09-29

申请号：US12193401

申请日：2008-08-18

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.

摘要翻译： 一种用于向集成电路产生时钟信号的时钟信号发生器。 时钟信号发生器包括适于基于参考时钟信号产生多个相互延迟的时钟相位的延迟锁定环路。 延迟锁定环路还适于响应于第一控制信号而选择多个时钟相位中的一个作为延迟锁定环路的输出信号，其中所述输出信号是第一时钟信号。 时钟信号发生器还包括反相器，被配置为产生输出信号的反相;以及多路复用器单元，其被配置为响应于时钟转换信号，将输出信号或反相输出作为第二时钟信号 。

公开(公告)号：US20050083219A1

公开(公告)日：2005-04-21

申请号：US10972947

申请日：2004-10-25

申请人： Ola Andersson ,  Jacob Wikner

发明人： Ola Andersson ,  Jacob Wikner

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03M1/66 ,  H03M1/74

CPC分类号： H03M1/1033 ,  H03M1/742

摘要： The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n−1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

摘要翻译： 输入到电流转向数模转换器（49）的值X（n）在实际转换之前被修改（41），以补偿数模转换器的转换误差。 输入值根据数模转换器的型号（43）进行修改，其中数模转换器Y（n）的每个输出值是与各个输入成正比的期望值的和 值和错误。 该误差是稳定输出值的乘积，即期望值与由数模转换器实际提供的先前输出值Y（n-1）之间的差异以及仅作为功能的相对步进误差 并存储在表中。 相对步进误差也可以是先前输出信号和先前输入信号的函数。 该模型具有低复杂度，适用于片上实现。

公开(公告)号：US20090207059A1

公开(公告)日：2009-08-20

申请号：US12279437

申请日：2007-01-18

申请人： Jacob Wikner

发明人： Jacob Wikner

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/186

摘要： An analog-to-digital converter (1). The analog to digital converter (1) comprises a first range-control unit (100) adapted to generate a first range-control value for controlling a size of an input range of the analog-to-digital converter (1). The analog to digital converter further comprises a second range-control unit (200) adapted to generate a second range-control value for controlling a midpoint of the input range. Further, the analog-to-digital converter (1) comprises a reference-level unit (300) operatively connected to the first range-control unit (100) and the second range-control unit (200). The reference-level unit (300) is arranged to generate a plurality of reference levels at least based on the first and the second range-control value. The analog-to-digital converter further comprises a comparison unit (400) operatively connected to the second range-control unit (200) and the reference-level unit (300). The comparison unit (400) is arranged to perform at least one comparison between a difference between an analog input value of the analog-to-digital converter (1) and the second range-control value and individual reference levels of the plurality of reference levels. The comparison unit (400) is further arranged to generate a digital output value of the analog-to-digital converter (1) based on the at least one comparison.

摘要翻译： 一个模拟 - 数字转换器（1）。 模数转换器（1）包括适于产生用于控制模数转换器（1）的输入范围的大小的第一范围控制值的第一范围控制单元（100）。 模数转换器还包括适于产生用于控制输入范围的中点的第二范围控制值的第二范围控制单元（200）。 此外，模数转换器（1）包括可操作地连接到第一范围控制单元（100）和第二范围控制单元（200）的参考级单元（300）。 参考级单元（300）被布置成至少基于第一和第二范围控制值来生成多个参考电平。 模数转换器还包括可操作地连接到第二范围控制单元（200）和参考级单元（300）的比较单元（400）。 比较单元（400）被布置成执行模数转换器（1）的模拟输入值与第二范围控制值之间的差异与多个参考电平的单独参考电平之间的至少一个比较 。 比较单元（400）还被布置成基于至少一个比较来产生模数转换器（1）的数字输出值。

公开(公告)号：US06946983B2

公开(公告)日：2005-09-20

申请号：US10972947

申请日：2004-10-25

申请人： Ola Andersson ,  Jacob Wikner

发明人： Ola Andersson ,  Jacob Wikner

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03M1/66 ,  H03M1/74

CPC分类号： H03M1/1033 ,  H03M1/742

摘要： The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n−1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.