公开(公告)号：US5818770A

公开(公告)日：1998-10-06

申请号：US979302

申请日：1997-11-26

申请人： Jae-Chul Kim ,  Choong-Keun Kwak

发明人： Jae-Chul Kim ,  Choong-Keun Kwak

IPC分类号： G11C11/407 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/10

摘要： The present invention relates to a circuit and method for write recovery control for suppressing malfunctions during a write recovery operation. The circuit is for use in a semiconductor memory device including a plurality of memory cells connected in a matrix form to a plurality of word lines and paired bit lines. The circuit comprises a variable load circuit connected to the bit lines, for controlling the voltage level of the bit lines in response to a write enable signal, a word line selector for selecting a predetermined word line in response to an input address, and a delay controller for providing a delay control signal to the word line selector so as to delay activation of the word line selector during the write recovery operation.

摘要翻译： 本发明涉及一种用于在写入恢复操作期间抑制故障的写恢复控制的电路和方法。 该电路用于包括以矩阵形式连接到多条字线和成对位线的多个存储单元的半导体存储器件。 电路包括连接到位线的可变负载电路，用于响应于写使能信号来控制位线的电压电平，用于响应于输入地址选择预定字线的字线选择器和延迟 控制器，用于向字线选择器提供延迟控制信号，以便在写恢复操作期间延迟字线选择器的激活。

公开(公告)号：US5576999A

公开(公告)日：1996-11-19

申请号：US491348

申请日：1995-06-30

申请人： Jae-Chul Kim ,  Choong-Keun Kwak

发明人： Jae-Chul Kim ,  Choong-Keun Kwak

IPC分类号： G11C29/00 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/48

摘要： A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.

摘要翻译： 具有用于存储数据的正常存储单元阵列的半导体存储器件的冗余电路，用于修复正常存储器中的故障单元的冗余存储单元，单元阵列，用于接收地址和指定正常存储单元的正常解码器，冗余 用于选择冗余存储器单元的解码器。 电路包括由控制时钟控制的控制部分，并且具有用于编程要应用的地址的失败地址的熔丝，由控制部分的输出信号控制的发送部分，并且具有用于输出地址的第一路径 与地址同相，以及用于输出地址与地址异相的第二路径，从而在修复之前选择第一路径以通过正常和冗余解码器选择正常存储器单元和冗余存储器单元，并且切断熔丝 对应于故障地址并且在修复期间选择第二路径以通过冗余解码器选择冗余存储器单元，从而在老化测试期间能够老化正常存储器单元和冗余存储器单元。

公开(公告)号：US07796425B2

公开(公告)日：2010-09-14

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C11/4193 ,  G11C11/4197

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US20080212362A1

公开(公告)日：2008-09-04

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US07315469B2

公开(公告)日：2008-01-01

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C7/22

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。

公开(公告)号：US20060274574A1

公开(公告)日：2006-12-07

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US07064601B2

公开(公告)日：2006-06-20

申请号：US09955458

申请日：2001-09-18

申请人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G05F1/46

CPC分类号： G05F3/262

摘要： A reference voltage generating circuit includes a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal in which the current mirror circuit is operated in response to a voltage level of the second current path, a reference voltage output node for providing a reference voltage and being located on the second current path, an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device, and a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region.

公开(公告)号：US20060050548A1

公开(公告)日：2006-03-09

申请号：US11220294

申请日：2005-09-06

申请人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

发明人： Hyung-Rok Oh ,  Baek-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

摘要翻译： 半导体存储器件补偿漏电流。 多个存储单元设置在字线和位线的交点处。 多个虚拟单元被连接到至少一个虚拟位线。 泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。 读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。 存储器件是包含相变材料的相变存储器件。 半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

公开(公告)号：US20050281106A1

公开(公告)日：2005-12-22

申请号：US11146513

申请日：2005-06-07

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C11/417

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

摘要翻译： 提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。 该装置包括用于提供第一电源电压的第一电源。 此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。 此外，该装置包括标准接地。 提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。 第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。 第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。 从而可以降低功率和芯片尺寸。

公开(公告)号：US06657264B2

公开(公告)日：2003-12-02

申请号：US09940733

申请日：2001-08-28

申请人： Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L2994

CPC分类号： H01L27/0921 ,  H01L27/0266

摘要： A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.