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    Semiconductor memory device having local sense amplifier with on/off control
    2.
    发明授权
    Semiconductor memory device having local sense amplifier with on/off control 有权
    具有开/关控制的本地读出放大器的半导体存储器件

    公开(公告)号：US07855926B2

    公开(公告)日：2010-12-21

    申请号：US11188184

    申请日：2005-07-20

    申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    IPC分类号： G11C7/00 ,  G11C7/02

    CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

    摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

    摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF
    3.
    发明申请
    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
    高速相位调整数据速率（QDR）收发器及其方法

    公开(公告)号：US20070206428A1

    公开(公告)日：2007-09-06

    申请号：US11612800

    申请日：2006-12-19

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

    摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

    Semiconductor memory device having local sense amplifier with on/off control
    4.
    发明申请
    Semiconductor memory device having local sense amplifier with on/off control 有权
    具有开/关控制的本地读出放大器的半导体存储器件

    公开(公告)号：US20060028888A1

    公开(公告)日：2006-02-09

    申请号：US11188184

    申请日：2005-07-20

    申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

    摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

    摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

    Sense amplifier and semiconductor memory device using it
    5.
    发明授权
    Sense amplifier and semiconductor memory device using it 有权
    感应放大器和使用它的半导体存储器件

    公开(公告)号：US08374043B2

    公开(公告)日：2013-02-12

    申请号：US12453199

    申请日：2009-05-01

    申请人： Hyun-Bae Lee ,  Sang-Woong Shin

    发明人： Hyun-Bae Lee ,  Sang-Woong Shin

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C11/4091

    摘要： A sense amplifier having a pre-amplifier and a main-amplifier is disclosed. The pre-amplifier is connected to paired data line, senses and amplifies data on the paired data line using voltage mode and outputting a pair of differential signal. The main-amplifier is connected to the paired data line, senses and amplifies data on the paired data line using current mode and generating a first amplified signal, senses and amplifies the first amplified signal using voltage mode in response to the pair of differential signal, and outputting an amplified data.

    摘要翻译： 公开了一种具有前置放大器和主放大器的读出放大器。 前置放大器连接到成对的数据线，使用电压模式感测和放大配对数据线上的数据，并输出一对差分信号。 主放大器连接到成对数据线，使用当前模式感测和放大配对数据线上的数据，并产生第一放大信号，响应于该对差分信号，使用电压模式来感测和放大第一放大信号， 并输出放大数据。

    CMOS inverter cell
    8.
    发明申请
    CMOS inverter cell 审中-公开
    CMOS反相器电池

    公开(公告)号：US20070075368A1

    公开(公告)日：2007-04-05

    申请号：US11503819

    申请日：2006-08-14

    申请人： Hyuk-Joon Kwon ,  Sang-Woong Shin

    发明人： Hyuk-Joon Kwon ,  Sang-Woong Shin

    IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： A CMOS inverter cell having a small horizontal length which is reduced by substituting metal lines for supplying data signals to gates with a connection pattern which is mounted in one end of a supply voltage area of the CMOS inverter cell and is made of the same material as the gate. Data is supplied to the gates through at least one side of the CMOS inverter cell. A single gate pattern or a plurality of different gate patterns may be used.

    摘要翻译： 具有小水平长度的CMOS反相器单元，其通过用金属线替代金属线来减少，以将数据信号提供给具有安装在CMOS反相器单元的电源电压区域的一端中的连接图案的栅极，并且由与 大门。 数据通过CMOS反相器单元的至少一侧提供给栅极。 可以使用单个栅极图案或多个不同的栅极图案。

    Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same
    9.
    发明申请
    Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same 失效
    用于生成半导体存储器件的内部时钟的方法和使用其的半导体存储器件

    公开(公告)号：US20060239087A1

    公开(公告)日：2006-10-26

    申请号：US11388720

    申请日：2006-03-24

    申请人： Sang-Woong Shin

    发明人： Sang-Woong Shin

    IPC分类号： G11C7/00

    CPC分类号： G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

    摘要： In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array in the semiconductor memory device is output in synchronization with the external clock. A doubled sync clock synchronized with the external clock is generated by delaying the data clock. An internal clock is generated during operation in the high-speed test mode by delaying the doubled sync clock by a delay amount that corresponds to a delay amount experienced in generation of an internal clock in response to the external clock during operation in a normal mode. Accordingly, the high-speed test operation of the semiconductor memory device can be efficiently performed.

    摘要翻译： 在产生用于半导体存储器件的内部时钟的方法中，响应于外部时钟在高速测试模式下的操作期间产生双倍的时钟。 通过延迟双倍时钟来产生数据时钟，使得从半导体存储器件中的存储单元阵列读出的数据与外部时钟同步地输出。 通过延迟数据时钟产生与外部时钟同步的双倍同步时钟。 通过将双倍同步时钟延迟一个对应于在正常模式下操作期间响应于外部时钟的内部时钟的产生中所经历的延迟量的延迟量，在内部时钟在高速测试模式期间产生。 因此，可以有效地执行半导体存储器件的高速测试操作。

    Semiconductor memory testing device and test method using the same
    10.
    发明申请
    Semiconductor memory testing device and test method using the same 有权

    公开(公告)号：US20060163572A1

    公开(公告)日：2006-07-27

    申请号：US11336331

    申请日：2006-01-20

    申请人： Tae-Jin Jeong ,  Sang-Woong Shin

    发明人： Tae-Jin Jeong ,  Sang-Woong Shin

    IPC分类号： H01L21/66 ,  H01L23/58

    CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/56004 ,  G11C29/56012 ,  G11C2029/3602 ,  G11C2029/5602

    摘要： A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal clock signal having a relatively high frequency. The data input buffer buffers test pattern data provided in synchronization to the external clock signal to output the buffered test pattern data. The test data generator generates test data that is to be synchronized to the internal clock signal, using the outputted test pattern data based on a first or a second control signal. The data output buffer outputs the generated test data to a memory core of the semiconductor memory device. The test device generates various test data suitable for a memory test at a high operating speed.