Abstract:
A substrate transfer system includes a substrate transfer chamber between a substrate receiving port and a process chamber, the substrate transfer chamber providing a space for transferring a substrate between the substrate receiving port and the process chamber, and an ionizer within the substrate transfer chamber, the ionizer including a light source to irradiate electromagnetic waves having a predetermined radiation angle toward the substrate to eliminate static electricity of the substrate.
Abstract:
An ionizer includes a body extending in a first direction, a sheath gas nozzle installed in a lower portion of the body and having a spray hole and an electrode needle disposed within the spray hole to generate a corona discharge, a gas supply provided in the body and configured to be in fluid communication with the spray hole to supply a gas to the spray hole such that ions generated by the electrode needle are spayed out to the outside of the ionizer from the spray hole, and a pair of first and second guiding plates disposed at opposite sides of the sheath gas nozzle and extending downward from first and second sides of the body opposite to each other to guide the ions sprayed from the spray hole to be directed to a target. A semiconductor device may be manufactured using the ionizer.
Abstract:
A power generation structure according to an embodiment of the present invention comprises: terrain features spaced apart from each other at a first interval to thereby form a watercourse through which water can move in the front and rear directions; watercourse banks having a width narrower than the first interval and disposed on the watercourse to thereby respectively form equal-width watercourses having a constant width between the terrain features; a first water collecting bank disposed on the watercourse and formed in the shape of a tip extending from the front end of the watercourse bank on the basis of the moving direction of a tidal current, with the width being gradually decreased toward the front of the equal-width watercourse; and a second water collecting bank disposed on the watercourse and formed in the shape of a tip extending from the rear end of the watercourse bank on the basis of the moving direction of the tidal current, with the width being gradually decreased toward the rear of the equal-width watercourse.
Abstract:
A rechargeable battery including an electrode assembly, the electrode assembly including a positive electrode and a negative electrode; a case accommodating the electrode assembly; a cap plate coupled with the case; and a vent member welded to the cap plate, the vent member including a notch thereon, wherein a welded unit, by which the vent member and the cap plate are welded together, is separately formed toward a center of the cap plate in a thickness direction from an outer side of the cap plate so as to be spaced apart from the outer side of the cap plate.
Abstract:
According to an embodiment of the present invention, a tidal power generator may comprise: a plurality of channel levees which are arranged spaced apart from each other so as to form a channel having a constant width and which have a plurality of installation grooves, each being formed by recessing the surface facing the channel, wherein a tidal current can move forward/backward in the channel; a first water collection levee extending from the front end of the channel levees with reference to a movement direction of the tidal current and having a peak shape of which the width is gradually reduced towards the front side of the channel; a second water collection levee extending from the rear end of the channel levees with reference to the movement direction of the tidal current and having a peak shape of which the width is gradually reduced towards the rear side of the channel; and a waterwheel module which is inserted and installed in the installation groove and can generate power using movements of the tidal current.
Abstract:
An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.
Abstract:
In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.
Abstract:
A rechargeable battery having an electrode assembly formed by depositing/spiral-winding an positive electrode and a negative electrode on respective surfaces of a separator; a can including a pipe having a side seam portion to enclose the electrode assembly and a bottom plate bonded to a first opening of the pipe by a bottom seam portion to close and seal the first opening and facing an end portion of the electrode assembly; and a cap assembly bonded to a second opening of the pipe formed at the other side of the bottom plate to close and seal the second opening.
Abstract:
A semiconductor memory device used in a multiprocessor system is configured to perform a partial refresh operation based on the state of an access port instead of performing a refresh operation per memory bank via a bank address. The multiprocessor system includes a plurality of processors and the memory device includes a memory cell array and a plurality of ports correspondingly connected to the plurality of processors. The memory cell array includes a plurality of memory areas having predetermined memory capacity. Each of the plurality of memory areas is assigned to at least one of the plurality of ports. Each of the plurality of memory areas is accessed by any one of at least one corresponding processors through a corresponding port. A refresh controller is disposed between the plurality of ports and the plurality of memory areas and is configured to refresh at least one memory area assigned to a port connected to a processor which is in a predetermined operating mode.