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    Semiconductor memory devices, memory systems including the same and method of writing data in the same
    1.
    发明授权
    Semiconductor memory devices, memory systems including the same and method of writing data in the same 有权
    半导体存储器件，包括相同的存储器系统和在其中写入数据的方法

    公开(公告)号：US09164834B2

    公开(公告)日：2015-10-20

    申请号：US14160614

    申请日：2014-01-22

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/08 ,  G11C29/42

    CPC分类号： G06F11/1056 ,  G06F11/085 ,  G06F11/1008 ,  G11C29/42

    摘要： In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

    摘要翻译： 在一个实施例中，半导体器件包括存储器阵列和被配置为控制从存储器阵列读取数据和将数据写入存储器阵列的控制架构。 控制架构被配置为在存储器阵列中接收数据和码字位置，基于数据掩码选择所接收数据中的一个或多个数据单元，读取当前存储在存储器阵列中的码字位置处的码字，错误校正 读取码字以产生经校正的读取码字，从所选择的数据单元中选出的数据单元形成一个新的码字，并且将校验后的读取码字中的数据单元与所选择的数据单元不对应，并将新的代码字写入存储器阵列。

    Semiconductor memory device having three dimensional structure
    2.
    发明授权
    Semiconductor memory device having three dimensional structure 有权
    具有三维结构的半导体存储器件

    公开(公告)号：US07982221B2

    公开(公告)日：2011-07-19

    申请号：US12537521

    申请日：2009-08-07

    申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    IPC分类号： H01L29/76

    CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

    摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

    SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER OPERABLE AS A SEMI-LATCH TYPE AND A FULL-LATCH TYPE BASED ON TIMING AND DATA SENSING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER OPERABLE AS A SEMI-LATCH TYPE AND A FULL-LATCH TYPE BASED ON TIMING AND DATA SENSING METHOD THEREOF 有权
    具有感应放大器的半导体存储器件可以作为基于时序和数据传感方法的半锁式和全锁定型操作

    公开(公告)号：US20080165603A1

    公开(公告)日：2008-07-10

    申请号：US11969947

    申请日：2008-01-07

    申请人： Gong-Heum Han

    发明人： Gong-Heum Han

    IPC分类号： G11C7/00

    CPC分类号： G11C7/065

    摘要： A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.

    摘要翻译： 半导体存储器件包括存储单元阵列，具有以行和列排列的存储单元，行解码器选择行中的一个并激活所选择的行，位线读出放大器检测和放大耦合到所选择的存储单元的数据 通过列排列的数据总线读出放大器，检测和放大从位线读出放大器输出的数据;以及控制逻辑块，使读取操作中的位线和数据总线读出放大器工作，操作数据总线 在预定时间段内以半锁存型模式读出放大器，并且在预定时间段之后以全锁存类型模式操作数据总线读出放大器。

    Semiconductor memory device having reduced chip select output time
    4.
    发明授权
    Semiconductor memory device having reduced chip select output time 有权
    具有减少芯片选择输出时间的半导体存储器件

    公开(公告)号：US06714463B2

    公开(公告)日：2004-03-30

    申请号：US10251739

    申请日：2002-09-20

    申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

    发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

    IPC分类号： G11C700

    CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2281

    摘要： A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (tAA) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.

    摘要翻译： 半导体存储器件被提供以当外部芯片选择信号从非活动状态转换到激活状态时，响应于来自内部芯片选择缓冲器的内部芯片选择信号的激活而产生一系列脉冲信号。 利用这种配置，与现有技术相比，芯片选择输出时间（tco）更多地减少。 此外，芯片选择输出时间减小到等于地址访问时间（tAA），因为设计者可以控制芯片选择输出时间。 结果，可以减少半导体存储器件的整个访问时间。

    Memory devices that perform masked write operations and methods of operating the same
    5.
    发明授权
    Memory devices that perform masked write operations and methods of operating the same 有权
    执行屏蔽写操作的内存设备及其操作方法

    公开(公告)号：US09588840B2

    公开(公告)日：2017-03-07

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

    IPC分类号： G06F11/10 ,  G06F11/32

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

    MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME
    6.
    发明申请
    MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME 有权
    执行掩蔽写操作的记忆设备及其操作方法

    公开(公告)号：US20140317470A1

    公开(公告)日：2014-10-23

    申请号：US14225686

    申请日：2014-03-26

    申请人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

    发明人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Tae-young OH ,  Jang-woo RYU ,  Chan-yong LEE ,  Tae-seong JANG ,  Gong-heum HAN

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

    摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

    摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

    Semiconductor Memory Device Having Three Dimensional Structure
    7.
    发明申请
    Semiconductor Memory Device Having Three Dimensional Structure 审中-公开
    具有三维结构的半导体存储器件

    公开(公告)号：US20110266623A1

    公开(公告)日：2011-11-03

    申请号：US13185184

    申请日：2011-07-18

    申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    IPC分类号： H01L27/12

    CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

    摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ARRANGING AND MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ARRANGING AND MANUFACTURING THE SAME 有权
    半导体存储器件及其制造和制造方法

    公开(公告)号：US20080089163A1

    公开(公告)日：2008-04-17

    申请号：US11953289

    申请日：2007-12-10

    申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

    IPC分类号： G11C8/10

    CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

    摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

    Semiconductor memory device having reduced voltage coupling between bit lines
    10.
    发明申请
    Semiconductor memory device having reduced voltage coupling between bit lines 审中-公开
    具有降低位线之间的电压耦合的半导体存储器件

    公开(公告)号：US20070183234A1

    公开(公告)日：2007-08-09

    申请号：US11527088

    申请日：2006-09-26

    申请人： Gong-Heum Han ,  Chul-Sung Park ,  Hyung-Jin Kim ,  Byeong-Uk Yoo

    发明人： Gong-Heum Han ,  Chul-Sung Park ,  Hyung-Jin Kim ,  Byeong-Uk Yoo

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413

    摘要： An enhanced semiconductor memory device capable of eliminating or minimizing a cell data flip phenomenon caused by capacitive voltage coupling between bit lines in different bit line pairs. Each memory cell is connected to a word line and between a pair of bit line. A first precharging and equalizing circuit us connected to a first bit line pair and a second precharging and equalizing circuit us connected to an adjacent second bit line pair. The first and second precharging and equalizing circuit are activated independently and at different times in order to reduce voltage coupling between neighboring bit lines in different bit line pairs, thereby minimizing or eliminating a cell data flip phenomenon of a neighboring memory cell caused by voltage coupling between bit lines.

    摘要翻译： 一种增强的半导体存储器件，其能够消除或最小化由不同位线对中的位线之间的电容电压耦合引起的单元数据翻转现象。 每个存储单元连接到字线和一对位线之间。 我们连接到第一位线对的第一个预充电和均衡电路，以及连接到相邻的第二位线对的第二个预充电和均衡电路。 第一和第二预充电和均衡电路在不同时间独立激活，以便减少不同位线对中的相邻位线之间的电压耦合，从而最小化或消除由相邻存储器单元之间的电压耦合引起的单元数据翻转现象 位线。