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    Non-volatile memory device and method of manufacturing the same
    1.
    发明申请
    Non-volatile memory device and method of manufacturing the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20070063255A1

    公开(公告)日：2007-03-22

    申请号：US11492733

    申请日：2006-07-25

    申请人： Jae-Young Ahn ,  Ki-Hyan Hwang ,  Jin-Tae Noh ,  Hong-Suk Kim ,  Sung-Hae Lee

    发明人： Jae-Young Ahn ,  Ki-Hyan Hwang ,  Jin-Tae Noh ,  Hong-Suk Kim ,  Sung-Hae Lee

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7883 ,  H01L29/42332 ,  H01L29/66833

    摘要： In non-volatile memory devices and methods of manufacturing the non-volatile memory devices, a barrier layer having an upper portion of silicon nitride and a lower portion of silicon oxide is formed on a substrate by providing a silicon oxide layer on the substrate and performing a radical nitridation process on an upper portion of the silicon oxide layer. A trapping layer including silicon nitride is formed on the barrier layer. A blocking layer and a gate electrode layer are subsequently formed on the trapping layer. The gate electrode layer, the blocking layer, the trapping layer and the barrier layer are then partially etched to provide a gate structure.

    摘要翻译： 在非易失性存储器件和制造非易失性存储器件的方法中，在衬底上形成具有氮化硅上部和氧化硅下部的阻挡层，在衬底上提供氧化硅层并执行 在氧化硅层的上部进行自由基氮化处理。 在阻挡层上形成包括氮化硅的捕获层。 随后在捕获层上形成阻挡层和栅极电极层。 然后对栅极电极层，阻挡层，捕获层和阻挡层进行部分蚀刻以提供栅极结构。

    Gate structure and related non-volatile memory device and method
    4.
    发明申请
    Gate structure and related non-volatile memory device and method 审中-公开
    门结构及相关非易失性存储器件及方法

    公开(公告)号：US20070007583A1

    公开(公告)日：2007-01-11

    申请号：US11474429

    申请日：2006-06-26

    申请人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Jin-Tae Noh

    发明人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Jin-Tae Noh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L29/40117

    摘要： A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The single electrode is formed on the charge trap insulator, comprises a P-type impurity receptive semiconductor material, and is doped with P-type impurities.

    摘要翻译： 公开了一种适用于SONOS设备单元的门结构。 栅极结构包括电荷阱绝缘体和单个电极。 电荷陷阱绝缘体包括包含第一氧化硅层，氮化硅层和第二氧化硅层的多层结构。 单电极形成在电荷陷阱绝缘子上，包含P型杂质受体半导体材料，并掺杂有P型杂质。

    Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device
    9.
    发明授权
    Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device 有权
    电荷俘获电介质的制造方法和声波型非易失性半导体器件的制造方法

    公开(公告)号：US07510935B2

    公开(公告)日：2009-03-31

    申请号：US11468944

    申请日：2006-08-31

    申请人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Sang-Ryol Yang ,  Ki-Hyun Hwang

    发明人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Sang-Ryol Yang ,  Ki-Hyun Hwang

    IPC分类号： H01L21/8247

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  Y10S438/954

    摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.

    摘要翻译： 在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层 。 通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。 在氮化硅层上形成第二氧化物层。 因此，形成具有良好擦除特性的电荷俘获电介质。 在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING CHARGE TRAP LAYER WITH STACKED NITRIDE LAYERS
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING CHARGE TRAP LAYER WITH STACKED NITRIDE LAYERS 审中-公开
    半导体存储器件，包括带有堆叠的氮化物层的充电陷阱层

    公开(公告)号：US20080042192A1

    公开(公告)日：2008-02-21

    申请号：US11782858

    申请日：2007-07-25

    申请人： Kwangmin Park ,  Kihyun Hwang ,  Jae-Young Ahn ,  Seung-Hwan Lee ,  Ju-Wan Lim ,  Sung-Hae Lee

    发明人： Kwangmin Park ,  Kihyun Hwang ,  Jae-Young Ahn ,  Seung-Hwan Lee ,  Ju-Wan Lim ,  Sung-Hae Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  H01L29/4234

    摘要： A semiconductor memory device includes a semiconductor substrate, a tunnel insulating layer, charge trap layer, and a blocking layer. The tunnel insulating layer is on the semiconductor substrate. The charge trap layer is on the tunnel insulating layer and includes at least one pair of a first nitride layer with a higher trap density of holes than electrons and a second nitride layer with a higher trap density of electrons than holes. The blocking layer is on the charge trap layer opposite to the tunnel insulating layer. The first nitride layer may include silicon rich nitride, which may have a ratio of silicon to nitride of greater than 1 and less than or equal to 2. The second nitride layer may include aluminum nitride which may have a hexagonal crystalline structure.

    摘要翻译： 半导体存储器件包括半导体衬底，隧道绝缘层，电荷陷阱层和阻挡层。 隧道绝缘层位于半导体衬底上。 电荷陷阱层位于隧道绝缘层上，并且包括至少一对具有比电子陷阱密度高的第一氮化物层和具有比孔更高的电子陷阱密度的第二氮化物层。 阻挡层位于与隧道绝缘层相反的电荷陷阱层上。 第一氮化物层可以包括富硅氮化物，其可以具有大于1且小于或等于2的硅与氮化物的比率。第二氮化物层可以包括可以具有六方晶结构的氮化铝。