公开(公告)号：US09576949B2

公开(公告)日：2017-02-21

申请号：US13604299

申请日：2012-09-05

申请人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L29/66 ,  H01L27/07 ,  H01L27/02 ,  H01L29/872 ,  H01L29/06 ,  H02M3/07

CPC分类号： H01L27/0727 ,  H01L27/0222 ,  H01L29/0619 ,  H01L29/872 ,  H02M3/07

摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.

摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域 地区。 第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。 第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。

公开(公告)号：US20140062580A1

公开(公告)日：2014-03-06

申请号：US13604299

申请日：2012-09-05

申请人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Jam-Wem Lee ,  Wan-Yen Lin ,  Ming-Hsiang Song ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F3/02

CPC分类号： H01L27/0727 ,  H01L27/0222 ,  H01L29/0619 ,  H01L29/872 ,  H02M3/07

摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.

摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域 地区。 第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。 第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。

公开(公告)号：US20140094009A1

公开(公告)日：2014-04-03

申请号：US14106100

申请日：2013-12-13

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US08610220B2

公开(公告)日：2013-12-17

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20130307080A1

公开(公告)日：2013-11-21

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/088 ,  H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US08049250B2

公开(公告)日：2011-11-01

申请号：US12258946

申请日：2008-10-27

申请人： Ming-Hsiang Song ,  Jam-Wem Lee

发明人： Ming-Hsiang Song ,  Jam-Wem Lee

IPC分类号： H01L29/66

CPC分类号： H01L29/7436 ,  H01L27/0262

摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。 在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。 公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。 这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。

公开(公告)号：US20100103570A1

公开(公告)日：2010-04-29

申请号：US12258946

申请日：2008-10-27

申请人： Ming-Hsiang Song ,  Jam-Wem Lee

发明人： Ming-Hsiang Song ,  Jam-Wem Lee

IPC分类号： H02H9/00 ,  H01L29/74

CPC分类号： H01L29/7436 ,  H01L27/0262

摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。 在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。 公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。 这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。

公开(公告)号：US08759871B2

公开(公告)日：2014-06-24

申请号：US13176780

申请日：2011-07-06

申请人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

发明人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

IPC分类号： H01L29/66

CPC分类号： H01L27/0262

摘要： An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

摘要翻译： ESD保护电路包括IC的焊盘，耦合到用于缓冲数据的焊盘的电路，IC上的RC功率钳，以及第一和第二可硅可控整流器（SCR）电路。 RC电源钳位在正电源端子和接地端子之间。 第一SCR电路耦合在焊盘和正电源端子之间。 第一SCR电路具有耦合到RC功率钳位电路的第一触发输入。 第二SCR电路耦合在焊盘和接地端子之间。 第二SCR电路具有耦合到RC功率钳位电路的第二触发输入。 SCR电路中的至少一个包括栅极二极管，其被配置为选择性地在焊盘与正电源端子和接地端子之一之间提供短路或相对导电的电路径。

公开(公告)号：US20120037956A1

公开(公告)日：2012-02-16

申请号：US13282179

申请日：2011-10-26

申请人： Ming-Hsiang Song ,  Jam-Wem Lee

发明人： Ming-Hsiang Song ,  Jam-Wem Lee

IPC分类号： H01L27/06 ,  H01L29/73

CPC分类号： H01L29/7436 ,  H01L27/0262

摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。 在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。 公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。 这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。

公开(公告)号：US08963200B2

公开(公告)日：2015-02-24

申请号：US13527833

申请日：2012-06-20

申请人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

发明人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

IPC分类号： H01L29/45

CPC分类号： H01L27/0262 ,  H01L21/8248 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0921 ,  H01L29/0619 ,  H01L29/73 ,  H01L29/812

摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

摘要翻译： 提高保持电压SCR的方法和装置。 半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。 公开了用于形成装置的方法。