公开(公告)号：US06336183B1

公开(公告)日：2002-01-01

申请号：US09259140

申请日：1999-02-26

申请人： Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

发明人： Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F9312

CPC分类号： G06F9/3889 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

摘要翻译： 在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。 存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。 如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。 如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

公开(公告)号：US06658555B1

公开(公告)日：2003-12-02

申请号：US09435077

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

公开(公告)号：US06289428B1

公开(公告)日：2001-09-11

申请号：US09366599

申请日：1999-08-03

申请人： John Edward Derrick ,  Hung Qui Le ,  David James Shippy ,  Larry Edward Thatcher

发明人： John Edward Derrick ,  Hung Qui Le ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1202

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F12/04

摘要： A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.

摘要翻译： 公开了一种超标量处理器和方法，用于从未对准的数据地址有效地恢复。 处理器包括划分成多个可寻址存储器单元的存储器件。 多个可寻址存储器单元中的每一个具有第一多个字节的宽度。 确定存储器访问指令中包括的数据地址是否不对齐。 如果数据地址包括位于第一可寻址存储器单元中的第一数据段和位于第二可寻址存储器单元中的第二数据段，其中第一和第二数据段由可寻址存储器单元边界分隔，则该数据地址未对准。 响应于确定数据地址未对准，执行访问第一存储器单元并获得第一数据段的第一内部指令。 执行访问第二存储器单元并获得第二数据段的第二内部指令。 第一和第二数据段合并在一起。 由处理器执行的所有指令都受到存储器边界的约束，并且不会跨越存储器边界访问存储器。

公开(公告)号：US06543002B1

公开(公告)日：2003-04-01

申请号：US09435066

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1100

CPC分类号： G06F11/0721 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/0793 ,  G06F11/1405

摘要： A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.

公开(公告)号：US06298436B1

公开(公告)日：2001-10-02

申请号：US09327644

申请日：1999-06-08

申请人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

发明人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

IPC分类号： G06F9305

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3842

摘要： A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.

摘要翻译： 一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。 推测性地向处理器系统的执行单元发出第一预约指令。 在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令 订购。 响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令 相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

公开(公告)号：US06237081B1

公开(公告)日：2001-05-22

申请号：US09213319

申请日：1998-12-16

申请人： Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

发明人： Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

IPC分类号： G06F932

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.

摘要翻译： 处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。 执行单元（140）可接受并执行该指令或产生拒绝信号。 在发出每条指令之后，发出队列（144）保留发出的关键周期指令。 在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。 如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。 可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。 此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

公开(公告)号：US06336168B1

公开(公告)日：2002-01-01

申请号：US09259139

申请日：1999-02-26

申请人： Marlin Wayne Frederick, Jr. ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

发明人： Marlin Wayne Frederick, Jr. ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1316

CPC分类号： G06F9/30043 ,  G06F9/3824

摘要： Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

摘要翻译： 在加载存储单元中执行多个加载指令的流水线和并行执行。 当第一个加载指令引起高速缓存未命中并继续从系统存储器层次结构检索加载数据时，寻址相同加载数据的第二加载指令将被合并到第一加载指令中，以便从系统内存层次结构返回的数据为 发送到注册与第一和第二加载指令相关联的文件。 结果，第二加载指令不必等待，直到在数据高速缓存中写入和验证加载数据。

公开(公告)号：US06490653B1

公开(公告)日：2002-12-03

申请号：US09325397

申请日：1999-06-03

申请人： Robert Alan Cargnoni ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

发明人： Robert Alan Cargnoni ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1208

CPC分类号： G06F9/383 ,  G06F9/3842

摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.

摘要翻译： 公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。 处理系统包括主缓存和二级缓存。 所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。 该方法和系统包括确定第一指令是否在二级高速缓存内。 所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。 根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成 的周期。 在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。 问题队列使用信号在最佳时间发出相关指令。 如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

公开(公告)号：US5931957A

公开(公告)日：1999-08-03

申请号：US829669

申请日：1997-03-31

申请人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/00 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3834 ,  G06F9/3861

摘要： To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

摘要翻译： 为了支持关于存储指令执行无序的加载指令，实现了一种机制来检测（和校正）在逻辑上先前的存储指令之前执行的加载指令的发生，并且其中加载指令接收数据为 由存储指令修改之前的位置，以及加载指令的正确数据，包括来自存储指令的字节。 另外，为了执行与加载指令无序的存储指令，实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。 此外，为了支持相对于彼此执行的无序执行的加载指令，实现一种机制以确保任何一对加载指令（其访问至少一个共同的字节）返回数据与执行加载指令一致 为了。

公开(公告)号：US06901540B1

公开(公告)日：2005-05-31

申请号：US09435868

申请日：1999-11-08

申请人： T. W. Griffith, Jr. ,  Larry Edward Thatcher

发明人： T. W. Griffith, Jr. ,  Larry Edward Thatcher

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1016

摘要： A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations. In this embodiment, the load/store unit invokes the address translation unit to translate the effective address only if the effective address misses in the ERAT. The LSU may suitably include an ERAT miss queue (EMQ) adapted to retain an effective address that misses in the ERAT until the address translation unit completes the translation process. In this embodiment, the EMQ is configured to issue a TLB parity error interrupt signal to initiate the TLB parity error interrupt routine. In one embodiment, the TLB interrupt routine loads a data address register (DAR) of the microprocessor with the effective address of the instruction that resulted in the parity error. The TLB interrupt routine may further set a data storage interrupt routine status register (DSISR) to indicate the TLB parity error.

摘要翻译： 公开了一种用于处理诸如TLB的地址转换设施中的奇偶校验错误的微处理器，数据处理系统和方法。 微处理器包括被配置为生成与加载/存储指令相关联的有效地址的加载/存储单元。 一种地址转换单元，适于使用翻译后备缓冲器（TLB）将有效地址转换为实际地址。 地址转换单元包括奇偶校验器，其被配置为验证由TLB生成的实际地址的奇偶校验，并且当真实地址包含奇偶校验错误时向该加载存储单元发信号。 加载存储单元被配置为响应于来自翻译单元的信号而启动TLB奇偶校验错误中断程序。 在一个实施例中，TLB中断例程选择性地使包含奇偶校验错误的TLB条目失效。 加载/存储单元优选地包括包含一组地址转换的有效到真实地址表（ERAT）。 在本实施例中，加载/存储单元仅在ERAT中的有效地址丢失时才调用地址转换单元来翻译有效地址。 LSU可以适当地包括适于保留在ERAT中遗漏的有效地址的ERAT未命中队列（EMQ），直到地址转换单元完成翻译过程。 在本实施例中，EMQ被配置为发出TLB奇偶校验错误中断信号以启动TLB奇偶校验错误中断程序。 在一个实施例中，TLB中断例程用导致奇偶校验错误的指令的有效地址加载微处理器的数据地址寄存器（DAR）。 TLB中断程序还可以设置数据存储中断程序状态寄存器（DSISR）以指示TLB奇偶校验错误。