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    Voltage ratio regulator circuit for a spacer electrode of a flat panel display screen
    2.
    发明授权
    Voltage ratio regulator circuit for a spacer electrode of a flat panel display screen 有权
    用于平板显示屏的间隔电极的电压比调节器电路

    公开(公告)号：US6153986A

    公开(公告)日：2000-11-28

    申请号：US470674

    申请日：1999-12-23

    Applicant: James C. Dunphy ,  Donald R. Schropp, Jr.

    Inventor： James C. Dunphy ,  Donald R. Schropp, Jr.

    IPC: G09G3/20 ,  G05F1/10 ,  G09G3/22 ,  H01J29/02 ,  H01J31/12 ,  G05F1/00

    CPC classification number: G09G3/22 ,  H01J29/028 ,  H01J31/127 ,  G09G2300/043 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645

    Abstract: A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together. The spacer electrode at Ve and the high voltage supply at Vh are both coupled to a voltage ratio regulator circuit which maintains the ratio (Ve/Vh) using voltage dividers, an operational amplifier and other circuitry. The voltage ratio regulator compensates for variations in voltage supply performance. The time constants of the voltage ratio regular circuit is tuned to be near or slightly faster than the time constant of the inherent resistance and capacitance of the spacer wall. The invention can also correct for other sources of the voltage error on the spacer walls. The invention improves the electron path accuracy for pixels located near spacer walls.

    Abstract translation: 一种用于平板显示屏的间隔电极的电压比调节器电路。 在场致发射显示器（FED）器件的一个实施方案中，在高电压（Vh）面板和背板之间插入薄间隔壁，以在两者之间形成真空来固定这些结构。 面板上的磷光体层接收从背板（阴极）离散的电子发射区域选择性发射的电子，从而在面板上形成图像。 作为由荧光体层释放的能量的结果，面板相对于背板加热，从而沿着间隔壁产生温度梯度。 每个间隔壁的顶部在温度升高时变得更加导电，并且用于吸引向面板发射的电子。 为了抵抗这种吸引力，沿着每个间隔壁沿着背板上方的高度d放置间隔电极并保持在一个电压Ve。 所有间隔壁的电极连接在一起。 Ve处的间隔电极和Vh处的高电压源均耦合到使用分压器，运算放大器和其他电路保持比率（Ve / Vh）的电压比调节器电路。 电压比调节器补偿电压供应性能的变化。 电压比常规电路的时间常数调整为接近或略快于间隔壁的固有电阻和电容的时间常数。 本发明还可以校正间隔壁上的电压误差的其它来源。 本发明改善了靠近隔离墙的像素的电子路径精度。

    Voltage ratio regulator circuit for a spacer electrode of a flat panel display screen
    3.
    发明授权
    Voltage ratio regulator circuit for a spacer electrode of a flat panel display screen 失效

    公开(公告)号：US6051937A

    公开(公告)日：2000-04-18

    申请号：US87268

    申请日：1998-05-29

    Applicant: James C. Dunphy ,  Donald R. Schropp, Jr.

    Inventor： James C. Dunphy ,  Donald R. Schropp, Jr.

    IPC: G09G3/20 ,  G05F1/10 ,  G09G3/22 ,  H01J29/02 ,  H01J31/12 ,  G05F1/00

    CPC classification number: G09G3/22 ,  H01J29/028 ,  H01J31/127 ,  G09G2300/043 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645

    Abstract: A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together. The spacer electrode at Ve and the high voltage supply at Vh are both coupled to a voltage ratio regulator circuit which maintains the ratio (Ve/Vh) using voltage dividers, an operational amplifier and other circuitry. The voltage ratio regulator compensates for variations in voltage supply performance. The time constants of the voltage ratio regular circuit is tuned to be near or slightly faster than the time constant of the inherent resistance and capacitance of the spacer wall. The invention can also correct for other sources of the voltage error on the spacer walls. The invention improves the electron path accuracy for pixels located near spacer walls.

    Flat-panel display with intensity control to reduce light-centroid shifting
    4.
    发明授权
    Flat-panel display with intensity control to reduce light-centroid shifting 有权
    平板显示屏具有强度控制，减少轻质心跳

    公开(公告)号：US06414428B1

    公开(公告)日：2002-07-02

    申请号：US09302698

    申请日：1999-04-30

    Applicant: Donald R. Schropp, Jr. ,  John E. Field ,  James C. Dunphy ,  Lawrence S. Pan ,  David L. Morris ,  Ronald S. Besser ,  Christopher J. Spindt

    Inventor： Donald R. Schropp, Jr. ,  John E. Field ,  James C. Dunphy ,  Lawrence S. Pan ,  David L. Morris ,  Ronald S. Besser ,  Christopher J. Spindt

    IPC: H01J162

    CPC classification number: H01J29/028 ,  H01J29/467 ,  H01J29/481 ,  H01J31/127 ,  H01J2201/025 ,  H01J2329/8625

    Abstract: The intensity at which electrons emitted by a first plate structure (10) in a flat-panel display strike a second plate structure (12) for causing it to emit light is controlled so as to reduce image degradation that could otherwise arise from undesired electron-trajectory changes caused by effects such as the presence of a spacer system (14) between the plate structures. An electron-emissive region (20) in the first plate structure typically contains multiple laterally separated electron-emissive portions (201 and 202) for selectively emitting electrons. An electron-focusing system in the first plate structure has corresponding focus openings (42P1 and 42P2) through which electrons emitted by the electron-emissive portions respectively pass. Upon being struck by the so-emitted electrons, a light-emissive region (22) in the second plate structure emits light to produce at least part of a dot of the display's image.

    Abstract translation: 控制由平板显示器中的第一板结构（10）发射的电子撞击用于使其发光的第二板结构（12）的强度，以便减少否则可能由不期望的电子发射引起的图像劣化， 由诸如板结构之间的隔离系统（14）的影响引起的轨迹变化。 第一板结构中的电子发射区（20）通常包含用于选择性地发射电子的多个横向分离的电子发射部分（201和202）。 第一板结构中的电子聚焦系统具有相应的聚焦开口（42P1和42P2），电子发射部分发射的电子分别通过该开口。 在被所发射的电子撞击时，第二板结构中的发光区域（22）发光，以产生显示器图像的至少一部分点。

    System and method for reducing visible speckle in a projection visual display system
    6.
    发明授权
    System and method for reducing visible speckle in a projection visual display system 有权
    用于减少投影视觉显示系统中可见斑点的系统和方法

    公开(公告)号：US08031403B2

    公开(公告)日：2011-10-04

    申请号：US11948881

    申请日：2007-11-30

    Applicant: James C. Dunphy ,  Stephen W. Marshall

    Inventor： James C. Dunphy ,  Stephen W. Marshall

    IPC: G02B5/02 ,  G02B26/00 ,  G02B26/08 ,  G03H1/02 ,  G03B21/14 ,  H01J3/14

    CPC classification number: G03B21/56

    Abstract: The invention provides an apparatus for reducing speckle in a projection visual display (PVD) system, a method of reducing visible speckle in a PVD system and a PVD system incorporating the method or apparatus. In one embodiment, the apparatus includes a diffuser interposable in an optical path of a PVD system and a diffuser actuator having a single drive axis configured to cause the diffuser to travel in a lissajous curve at least partially transverse to the optical path.

    Abstract translation: 本发明提供一种用于减少投影视觉显示（PVD）系统中的斑点的装置，减少PVD系统中的可见斑点的方法以及包含该方法或装置的PVD系统。 在一个实施例中，该装置包括在PVD系统的光路中可插入的漫射器和具有单个驱动轴的扩散器致动器，该单个驱动轴构造成使漫射器至少部分地横向于光路穿过假丝带曲线。

    Method for minimizing zero current shift in a flat panel display
    8.
    发明授权
    Method for minimizing zero current shift in a flat panel display 失效
    使平板显示器中的零电流偏移最小化的方法

    公开(公告)号：US06722935B1

    公开(公告)日：2004-04-20

    申请号：US09895531

    申请日：2001-06-29

    Applicant: James C. Dunphy ,  Christopher J. Spindt

    Inventor： James C. Dunphy ,  Christopher J. Spindt

    IPC: H01J924

    CPC classification number: H01J29/467 ,  H01J9/185 ,  H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/865 ,  H01J2329/8655 ,  H01J2329/8665

    Abstract: In a flat-panel display structure having a spacer with laterally segmented face electrodes, one embodiment of the present invention defines the length of the laterally segmented face electrode sections to minimize zero current shift variation in electron trajectories. Advantageously, the present embodiment of the invention prevents image quality degradation. In one embodiment, values for variation in the uniformity of and dicing tolerance are combined to calculate a design optimum for the length of laterally segmented face electrodes. Zero current shift variation from fluctuations in wall resistance falls off with the length of laterally segmented face electrodes. Zero current shift due to first order angular alignment during dicing varies linearly with the dashed electrode length. In one embodiment of the present invention, an optimal value is calculated by combining these effects to minimize zero current shift. Advantageously, in one embodiment, the electrode segments are individually testable.

    Abstract translation: 在具有具有横向分割的面电极的间隔件的平板显示器结构中，本发明的一个实施例限定了横向分割的面电极部分的长度，以最小化电子轨迹中的零电流偏移变化。 有利地，本发明的本实施例防止图像质量下降。 在一个实施例中，组合均匀度和切割公差的变化值，以计算横向分割的面电极的长度的最佳设计。 零电流偏移随壁面电阻波动的变化随着横向分段面电极的长度而下降。 在切割期间由于一阶角度对准导致的零电流偏移随虚线电极长度线性变化。 在本发明的一个实施例中，通过组合这些效应来计算最佳值以将零电流偏移最小化。 有利地，在一个实施例中，电极段是可单独测试的。

    Interface layer for the fabrication of electronic devices
    9.
    发明授权
    Interface layer for the fabrication of electronic devices 失效
    接口层用于制造电子设备

    公开(公告)号：US07315068B2

    公开(公告)日：2008-01-01

    申请号：US11077240

    申请日：2005-03-09

    Applicant: Scott Haubrich ,  Klaus Kunze ,  James C. Dunphy ,  Chris Gudeman ,  Joerg Rockenberger ,  Fabio Zurcher ,  Nassrin Sleiman ,  Mao Takashima ,  Chris Spindt

    Inventor： Scott Haubrich ,  Klaus Kunze ,  James C. Dunphy ,  Chris Gudeman ,  Joerg Rockenberger ,  Fabio Zurcher ,  Nassrin Sleiman ,  Mao Takashima ,  Chris Spindt

    IPC: H01L29/94

    CPC classification number: H01L27/1292

    Abstract: The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the substrate and preferably provides good adhesion of the active device layer to the substrate. The active device layer is preferably fashioned from a nanoparticle ink solution that is patterned using embossing methods or other suitable printing and/or imaging methods. The active device layer is preferably patterned into an array of gate structures suitable for the fabrication of thin film transistors and the like.

    Abstract translation: 本发明涉及用于制造具有薄的各向异性导电层界面层的电子器件的方法，所述薄的各向异性导电层界面层形成在衬底和优选图案化导电层的有源器件层之间。 界面层优选地在有源器件层和衬底之间提供欧姆和/或整流接触，并且优选地提供有源器件层与衬底的良好粘附。 活性器件层优选由使用压花方法或其它合适的印刷和/或成像方法图案化的纳米颗粒油墨溶液形成。 有源器件层优选地被图案化成适于制造薄膜晶体管等的栅极结构的阵列。

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