公开(公告)号：US20070142175A1

公开(公告)日：2007-06-21

申请号：US11614063

申请日：2006-12-20

Applicant: Curt Morgan ,  James Dawson

Inventor： Curt Morgan ,  James Dawson

IPC: A63B15/02 ,  A63B26/00

CPC classification number: A63B21/068 ,  A63B21/0622 ,  A63B21/0628 ,  A63B22/0076 ,  A63B22/0089 ,  A63B22/02 ,  A63B22/0605 ,  A63B23/0211 ,  A63B2210/56

Abstract: Various embodiments of the invention are directed towards an automated mechanism for collapsing exercise equipment. The invention discloses electromechanical means for processing an input signal and manipulating physical aspects of the exercise equipment such that the equipment collapses for easier storage or movement. The invention is adaptable to a wide range of electronic exercise equipment such as complete exercise systems, treadmills, exercise bicycles, sit-up devices, rowing machines, and other such devices.

Abstract translation: 本发明的各种实施例涉及一种用于塌缩运动器材的自动化机构。 本发明公开了一种用于处理输入信号并操纵锻炼设备的物理方面的机电装置，使得设备塌陷以便于存储或移动。 本发明适用于各种各样的电子锻炼设备，例如完整的运动系统，跑步机，运动自行车，仰卧起动装置，划船机和其他这样的装置。

公开(公告)号：US20060181950A1

公开(公告)日：2006-08-17

申请号：US11056315

申请日：2005-02-11

Applicant: John Davis ,  James Dawson ,  Donald Plass ,  Kenneth Reyer

Inventor： John Davis ,  James Dawson ,  Donald Plass ,  Kenneth Reyer

IPC: G11C8/00

CPC classification number: G11C11/418 ,  G11C8/10

Abstract: A memory decoding apparatus includes a plurality of local subarray support circuits associated with a memory subarray, and a common bus locally configured with respect to said plurality of local subarray support circuits, the common bus configured for synchronous activation of one or more of the plurality of local subarray support circuits.

Abstract translation: 存储器解码装置包括与存储器子阵列相关联的多个局部子阵列支持电路和相对于所述多个局部子阵列支持电路局部配置的公共总线，所述公共总线被配置为用于同步激活多个 本地子阵列支持电路。

公开(公告)号：US20090006477A1

公开(公告)日：2009-01-01

申请号：US12115759

申请日：2008-05-06

Applicant: Yasuo Oshita ,  Hidetsugu Obi ,  Hideki Matsuda ,  Yoshiyuki Kodama ,  Junji Ajioka ,  James Dawson ,  Michael Claypool ,  Christine Prentice ,  John Reaves

Inventor： Yasuo Oshita ,  Hidetsugu Obi ,  Hideki Matsuda ,  Yoshiyuki Kodama ,  Junji Ajioka ,  James Dawson ,  Michael Claypool ,  Christine Prentice ,  John Reaves

IPC: G06F17/30

CPC classification number: G06F21/62 ,  G06F17/30011

Abstract: Only the display device stores content files and a management device stores file management information. The content files are managed using the file management information. Because the management device does not store the actual content files, the security policy of an organization is not violated even if the management device is located outside the organization. Furthermore, because the display device stores the content files, the user desire to keep content files locally at hand is satisfied. Furthermore, because file management information consisting of small amounts of data is exchanged between the display system and the management device, the communication environment of the system does not need to be suitable to large data transmissions. Furthermore, because the management device stores the file management information, the storage capacity required by the management device is small.

Abstract translation: 只有显示装置存储内容文件，管理装置存储文件管理信息。 使用文件管理信息管理内容文件。 由于管理设备不存储实际的内容文件，即使管理设备位于组织外部，组织的安全策略也不会被侵犯。 此外，由于显示装置存储内容文件，所以希望用户期望在本地保留内容文件。 此外，由于在显示系统和管理装置之间交换由少量数据组成的文件管理信息，因此系统的通信环境不需要适合于大数据传输。 此外，由于管理装置存储文件管理信息，管理装置所需的存储容量小。

公开(公告)号：US20060179377A1

公开(公告)日：2006-08-10

申请号：US11054566

申请日：2005-02-09

Applicant: James Dawson ,  Thomas Knips ,  Donald Plass ,  Kenneth Reyer

Inventor： James Dawson ,  Thomas Knips ,  Donald Plass ,  Kenneth Reyer

IPC: G01R31/28

CPC classification number: G11C29/1201 ,  G11C11/41 ,  G11C29/40 ,  G11C29/48 ,  G11C29/802 ,  G11C2029/3602

Abstract: A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.

Abstract translation: 一种实现ABIST数据压缩和串行化的方法和装置，用于具有冗余的SRAM的内存自检。 该方法包括提供为一个故障数据输出断言的检测信号，两个故障数据输出和大于两个故障数据输出。 该方法还包括用对应的二进制表示值来单独编码每个相应的故障数据输出的故障位位置。 该方法还包括串行化提供检测信号和单独编码的结果，并将序列化的结果发送到单个故障总线上的冗余支持寄存器功能。

公开(公告)号：US20060171215A1

公开(公告)日：2006-08-03

申请号：US11046101

申请日：2005-01-28

Applicant: James Dawson ,  Donald Plass ,  Kenneth Reyer

Inventor： James Dawson ,  Donald Plass ,  Kenneth Reyer

IPC: G11C7/00

CPC classification number: G11C11/417 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C2207/002

Abstract: A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

Abstract translation: 半导体存储器件的位线选择装置包括选择性地耦合到全局位线对的第一局部位线对和第二本地位线对，第一和第二局部位线对中的每一个包括真位线和互补位线。 通过与其并联的n型通过器件和p型通过器件，每个真实位线选择性地耦合到公共真实节点，并且每个互补位线通过n型选择性地耦合到公共互补节点 通过装置和p型通过装置。

公开(公告)号：US11649687B1

公开(公告)日：2023-05-16

申请号：US17707042

申请日：2022-03-29

Applicant: James Dawson

Inventor： James Dawson

IPC: E21B23/01 ,  E21B17/10

CPC classification number: E21B23/01 ,  E21B17/1021 ,  E21B17/1078

Abstract: A high expansion anti-rotation anchor catcher includes a helical track positioned on an exterior surface of a tubular body. An expandable gripper cage is provided having an axially fixed hub mounted for rotation about the tubular body and an axially movable hub mounted for rotation about the tubular body. Pivoting linkages which support outwardly oriented grippers extend between the axially fixed hub and the axially movable hub. The axially movable hub has a track follower that engages the helical track on the exterior surface of the tubular body. Rotation of the tubular body in a first rotational direction causes the track follower to move along the helical track toward the axially fixed hub, thereby placing the expandable gripper cage in compression and causing the pivoting linkages and grippers to pivot outwardly away from the tubular body to secure the anchor in position.

公开(公告)号：US20060176760A1

公开(公告)日：2006-08-10

申请号：US11054176

申请日：2005-02-09

Applicant: Paul Bunce ,  John Davis ,  James Dawson ,  Donald Plass

Inventor： Paul Bunce ,  John Davis ,  James Dawson ,  Donald Plass

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/12

Abstract: A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.

Abstract translation: 为配置有多个存储器子阵列的存储器阵列提供全局和本地读取控制同步方法和系统。 解码地址信号以基于子阵列选择信号和累积子阵列选择信号来激活。 每当子阵列选择信号变为有效时，累积子阵列选择信号变为有效，因此累积子阵列选择信号的每个脉冲与子阵列选择信号的一个脉冲同步。 使用子阵列选择信号获得用于多个存储器子阵列的本地读取控制信号，并且使用累积子阵列选择信号获得用于存储器阵列的至少一个全局读取控制信号。 在一个示例中，存储器阵列具有分层位线架构。

公开(公告)号：US20060176081A1

公开(公告)日：2006-08-10

申请号：US11050895

申请日：2005-02-04

Applicant: James Dawson ,  Donald Plass ,  Kenneth Reyer

Inventor： James Dawson ,  Donald Plass ,  Kenneth Reyer

IPC: H03K19/084

CPC classification number: H03K19/0963

Abstract: A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

Abstract translation: 解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。 通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。

公开(公告)号：US20060174153A1

公开(公告)日：2006-08-03

申请号：US11050580

申请日：2005-02-03

Applicant: James Dawson ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

Inventor： James Dawson ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/227

Abstract: A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.

Abstract translation: 提供了一种时钟控制方法和装置，其采用从系统时钟和复位控制信号产生用于存储器阵列的阵列时钟的时钟控制电路。 复位控制信号是到时钟控制电路的多个输入控制信号之一。 当系统时钟低于预定频率阈值时，复位控制信号是阵列跟踪复位信号，其中阵列时钟的有效脉冲宽度是系统时钟频率无关的，当系统时钟高于预定频率阈值时， 复位控制信号是中周期复位信号，意味着阵列时钟的有效脉冲宽度取决于系统时钟。 提供旁路信号作为第三输入控制信号，当有效时，时钟控制电路输出反映系统时钟的阵列时钟。

公开(公告)号：US20220212588A1

公开(公告)日：2022-07-07

申请号：US17569649

申请日：2022-01-06

Applicant: James Dawson

Inventor： James Dawson

IPC: B60N3/06

Abstract: Automobile accessories, kits, and methods of use. An automobile accessory is a heel guard that can be applied to a floor and/or a floor mat within an interior of an automobile such as a car, a truck, a van, a bus, and the like. The heel guard may be secured to the floor and/or the floor mat to provide a layer of protection between the driver's shoe or foot and the floor and/or floor mat. The heel guard prevents damage to these surfaces due to friction produced by movement of the driver's foot during operation of the foot pedals of the automobile.