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公开(公告)号：US20150186320A1
公开(公告)日：2015-07-02
申请号：US14142208
申请日：2013-12-27
IPC分类号： G06F13/40
CPC分类号： G06F13/4068
摘要： A computing system can include an electronic device including a controller and a new form factor (NFF) receptacle. The computing system can also include a legacy-compatible adapter coupled to the NFF receptacle to couple the electronic device to a second electronic device. The second electronic device can include a legacy connector. The adapter can include a voltage converter to convert voltage signals between the NFF receptacle of the electronic device and the legacy connector of the second electronic device.
摘要翻译： 计算系统可以包括包括控制器和新形状因子（NFF）插座的电子设备。 计算系统还可以包括耦合到NFF插座的传统兼容适配器，以将电子设备耦合到第二电子设备。 第二电子设备可以包括传统连接器。 适配器可以包括电压转换器，用于将电子设备的NFF插座和第二电子设备的传统连接器之间的电压信号转换。
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公开(公告)号：US09362684B2
公开(公告)日：2016-06-07
申请号：US13997096
申请日：2011-12-14
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译： 方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。
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公开(公告)号：US20140237142A1
公开(公告)日：2014-08-21
申请号：US13995590
申请日：2011-09-30
CPC分类号： H04L41/0896 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.
摘要翻译： 互连设备的系统和方法可以包括具有一个或多个设备侧数据通道的输入/输出（IO）接口和用于接收带宽配置命令的收发机逻辑。 收发器逻辑还可以基于带宽配置命令来配置一个或多个设备侧数据通道的发送带宽。 此外，收发器逻辑可以基于带宽配置命令来配置一个或多个设备侧数据通道的接收带宽。
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公开(公告)号：US10089270B2
公开(公告)日：2018-10-02
申请号：US13995594
申请日：2011-10-17
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.
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公开(公告)号：US09804646B2
公开(公告)日：2017-10-31
申请号：US13995591
申请日：2011-10-17
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3203
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.
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公开(公告)号：US20130283070A1
公开(公告)日：2013-10-24
申请号：US13995591
申请日：2011-10-17
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3203
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.
摘要翻译： 互连设备的系统和方法可以包括具有集成稳压器的缓冲器的输入/输出（IO）连接器。 集成电压调节器可以包括第一电源输出和第二电源输出，其中IO连接器包括耦合到第一电源输出的IO电源触点。 IO连接器还可以包括耦合到第二电源输出的逻辑电源触点。 在一个示例中，主机设备可以向缓冲器发布功率管理命令，以便与第一电源输出独立地缩放第二电源输出。
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公开(公告)号：US09654342B2
公开(公告)日：2017-05-16
申请号：US13995590
申请日：2011-09-30
CPC分类号： H04L41/0896 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.
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8.发明申请UNIVERSAL IO CONNECTOR AND INTERFACE CAPABLE OF BOTH WIRED AND WIRELESS OPERATION 有权通用IO连接器和两个可以接线和无线操作的接口公开(公告)号：US20140242927A1
公开(公告)日：2014-08-28
申请号：US13995592
申请日：2011-11-11
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
IPC分类号： H04B1/40
CPC分类号： H04B1/40 , G06F13/4068 , G06F2213/0042
摘要： Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.
摘要翻译： 互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。 在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。
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9.发明申请公开(公告)号：US20140208126A1
公开(公告)日：2014-07-24
申请号：US13995596
申请日：2011-10-28
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3215 , G06F1/324 , G06F1/3265 , G06F1/3278 , G06F1/3296 , G06F13/14 , G09G5/006 , G09G5/18 , G09G2330/021 , Y02D10/126 , Y02D10/153 , Y02D10/157 , Y02D10/172 , Y02D50/20
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
摘要翻译： 互连设备的系统和方法可以包括具有一个或多个时钟电路的输入/输出（IO）接口，耦合到一个或多个时钟电路的电源以及在IO接口处接收速率调整命令的逻辑。 逻辑还可以被配置为响应于速率调整命令来调整IO接口的数据速率，并且响应于速率调整命令来调整电源的输出电压。
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公开(公告)号：US09791905B2
公开(公告)日：2017-10-17
申请号：US13995596
申请日：2011-10-28
CPC分类号： G06F1/26 , G06F1/266 , G06F1/3215 , G06F1/324 , G06F1/3265 , G06F1/3278 , G06F1/3296 , G06F13/14 , G09G5/006 , G09G5/18 , G09G2330/021 , Y02D10/126 , Y02D10/153 , Y02D10/157 , Y02D10/172 , Y02D50/20
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
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