公开(公告)号：US08105867B2

公开(公告)日：2012-01-31

申请号：US12468717

申请日：2009-05-19

申请人： George Matamis ,  Henry Chien ,  James K Kai ,  Takashi Orimoto ,  Vinod R Purayath ,  Er-Xuan Ping ,  Roy E Scheuerlein

发明人： George Matamis ,  Henry Chien ,  James K Kai ,  Takashi Orimoto ,  Vinod R Purayath ,  Er-Xuan Ping ,  Roy E Scheuerlein

IPC分类号： H01L21/00

CPC分类号： H01L21/20 ,  G11C13/0004 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

摘要翻译： 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

公开(公告)号：US20100124813A1

公开(公告)日：2010-05-20

申请号：US12468717

申请日：2009-05-19

申请人： George Matamis ,  Henry Chien ,  James K. Kai ,  Takashi Orimoto ,  Vinod R Purayath ,  Er-Xuan Ping ,  Roy E. Scheuerlein

发明人： George Matamis ,  Henry Chien ,  James K. Kai ,  Takashi Orimoto ,  Vinod R Purayath ,  Er-Xuan Ping ,  Roy E. Scheuerlein

IPC分类号： H01L21/20 ,  H01L21/3205

CPC分类号： H01L21/20 ,  G11C13/0004 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

摘要翻译： 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

公开(公告)号：US07915664B2

公开(公告)日：2011-03-29

申请号：US12105242

申请日：2008-04-17

申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

IPC分类号： H01L29/788

CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

公开(公告)号：US20090261398A1

公开(公告)日：2009-10-22

申请号：US12105242

申请日：2008-04-17

申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

IPC分类号： H01L29/788

CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

公开(公告)号：US08710481B2

公开(公告)日：2014-04-29

申请号：US13356047

申请日：2012-01-23

申请人： James K. Kai ,  Henry Chien ,  George Matamis ,  Vinod R. Purayath

发明人： James K. Kai ,  Henry Chien ,  George Matamis ,  Vinod R. Purayath

IPC分类号： H01L47/00

CPC分类号： H01L29/413 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1675

摘要： A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.

摘要翻译： 非易失性存储器件包括多个非易失性存储器单元。 每个非易失性存储单元包括第一电极，二极管操纵元件，与二极管操纵元件串联的存储元件，第二电极和宽度为15nm或更小的纳米轨道电极。

公开(公告)号：US20130187114A1

公开(公告)日：2013-07-25

申请号：US13356047

申请日：2012-01-23

申请人： James K. Kai ,  Henry Chien ,  George Matamis ,  Vinod R. Purayath

发明人： James K. Kai ,  Henry Chien ,  George Matamis ,  Vinod R. Purayath

IPC分类号： H01L21/822 ,  H01L45/00 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/413 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1675

摘要： A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.

摘要翻译： 非易失性存储器件包括多个非易失性存储器单元。 每个非易失性存储单元包括第一电极，二极管操纵元件，与二极管操纵元件串联的存储元件，第二电极和宽度为15nm或更小的纳米轨道电极。

公开(公告)号：US08207036B2

公开(公告)日：2012-06-26

申请号：US12242857

申请日：2008-09-30

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

公开(公告)号：US08383479B2

公开(公告)日：2013-02-26

申请号：US12840081

申请日：2010-07-20

申请人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L21/8247

CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

公开(公告)号：US20110020992A1

公开(公告)日：2011-01-27

申请号：US12840081

申请日：2010-07-20

申请人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

摘要翻译： 基于纳米结构的电荷存储区域包括在非易失性存储器件中，并与制造选择栅极和外围电路集成。 在存储器阵列区域和外围电路区域上的衬底上施加一个或多个纳米结构涂层。 提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。 在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层，以选择性地在衬底的有源区上形成纳米结构。 自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

公开(公告)号：US20100081267A1

公开(公告)日：2010-04-01

申请号：US12242857

申请日：2008-09-30

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

IPC分类号： H01L21/3205

CPC分类号： H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。