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    Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate
    5.
    发明授权
    Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate 失效
    制备用一种或多种IV族元素处理的IV族半导体衬底以形成能够抑制衬底中掺杂剂材料迁移的势垒区的方法

    公开(公告)号：US5858864A

    公开(公告)日：1999-01-12

    申请号：US939350

    申请日：1997-09-29

    申请人： Sheldon Aronowitz ,  James Kimball

    发明人： Sheldon Aronowitz ,  James Kimball

    IPC分类号： H01L21/265

    CPC分类号： H01L21/26506 ,  H01L21/26513

    摘要： Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

    摘要翻译： 描述了以与衬底中的掺杂区域预定间隔的单晶IV IV半导体衬底中的阻挡区域的形成，以防止或抑制掺杂剂材料通过阻挡区域从相邻掺杂区域的迁移。 通过将IV族材料注入到半导体衬底中至超过掺杂区域的深度的预定深度，可以在半导体中产生阻挡区域，以防止掺杂剂从掺杂区域迁移穿过阻挡区域。 用IV族材料处理单晶衬底以足以在半导体衬底中提供这种势垒区域的剂量和能级进行，但不足以导致半导体单晶晶格的非晶化（破坏） 基质。

    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
    6.
    发明授权
    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device 失效
    具有受控量的惰性气体离子的衬底，以减少形成PMOS器件的P-LDD区域的硼掺杂物的沟道和/或扩散

    公开(公告)号：US5717238A

    公开(公告)日：1998-02-10

    申请号：US677078

    申请日：1996-07-09

    申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/26506

    摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

    摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

    Electrostatic dust collection wand
    7.
    发明申请
    Electrostatic dust collection wand 审中-公开
    静电除尘魔杖

    公开(公告)号：US20060064826A1

    公开(公告)日：2006-03-30

    申请号：US10857154

    申请日：2004-09-27

    申请人： James Kimball

    发明人： James Kimball

    IPC分类号： A47L13/40

    CPC分类号： A47L13/40 ,  A47L13/38

    摘要： An electrostatic dust wand has a handle, a triboelectric charge generator, and a fibrous material. The triboelectric charge generator is coupled to the handle, and generates an electrostatic charge to attract dust particles to the cleaning implement. The fibrous material at least partially covers the triboelectric charge generator, to collect and to retain dust particles. The triboelectric charge generator has at least one movable member having a first triboelectric property, and an actuator for driving the at least one movable member. The electrostatic charge may be generated by movement of he at least one movable member against the fibrous material. Alternatively, or in addition, the electrostatic charge may be generated by relative movement of two members of the triboelectric charge generator against one another.

    摘要翻译： 静电防尘棒具有手柄，摩擦电荷发生器和纤维材料。 摩擦电荷发生器耦合到手柄，并产生静电荷以将尘埃颗粒吸引到清洁器具上。 纤维材料至少部分地覆盖摩擦电荷发生器，以收集和保留灰尘颗粒。 所述摩擦电荷发生器具有至少一个具有第一摩擦学特性的可移动部件和用于驱动所述至少一个可移动部件的致动器。 静电电荷可以通过使至少一个可动构件抵靠纤维材料移动而产生。 或者或另外，静电电荷可以通过摩擦电荷发生器的两个部件相对于彼此的相对运动而产生。

    Method of forming retrograde well structures and punch-through barriers using low energy implants
    8.
    发明授权
    Method of forming retrograde well structures and punch-through barriers using low energy implants 失效
    使用低能量植入物形成逆行井结构和穿通障碍的方法

    公开(公告)号：US5963801A

    公开(公告)日：1999-10-05

    申请号：US770109

    申请日：1996-12-19

    申请人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    发明人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L21/823892

    摘要： A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.

    摘要翻译： 通过使用低能离子注入机形成CMOS器件中的逆行阱。 将掺杂原子沿着与衬底的表面（具有<100>取向的衬底）正交的方向注入器件衬底的裸露表面。 可以在低于220keV的能量下进行井注入。 逆行井中的穿通屏障的链接植入物可以在植入物之后进行。 当衬底退火时，穿通屏障在逆行井的同时被激活。

    Vaporization and ionization of metals for use in semiconductor processing
    9.
    发明授权
    Vaporization and ionization of metals for use in semiconductor processing 失效
    用于半导体加工的金属的蒸发和电离

    公开(公告)号：US07084408B1

    公开(公告)日：2006-08-01

    申请号：US10697507

    申请日：2003-10-29

    申请人： James Kimball ,  Sheldon Aronowitz

    发明人： James Kimball ,  Sheldon Aronowitz

    IPC分类号： H01J27/00 ,  H01J37/08 ,  G21K5/10

    CPC分类号： H01J27/04 ,  C23C14/228 ,  C23C14/32 ,  C23C14/48

    摘要： Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

    摘要翻译： 用加热的惰性载气汽化和处理蒸发的金属元素或金属元素盐进行进一步处理的技术。 蒸发的金属元素或盐由加热至与蒸发温度相同的温度的惰性载气携带到加热的处理室。 金属或盐蒸气可以离子化（和注入）或沉积在基底上。 还提供了用于实现这些技术的装置，其包括载气加热室和加热处理室。

    FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
    10.
    发明授权
    FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements 失效
    具有轻掺杂漏极区域的FET，其被形成有反向和不对称的多个元件

    公开(公告)号：US06180470B2

    公开(公告)日：2001-01-30

    申请号：US08770046

    申请日：1996-12-19

    申请人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    发明人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S438/925

    摘要： Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

    摘要翻译： 通过修改器件的LDD区域边界处的电活性LDD掺杂剂的分布来增加短沟道NMOS器件的寿命。 通过在LDD区域的边界处注入反掺杂剂来修改LDD掺杂剂分布。 III族反掺杂剂如硼和IV族元素如硅改变LDD掺杂剂的活化性质。 掺杂剂分布在器件的n结处修改，以减少由器件的栅极和衬底限定的界面处的最大电场位移。 可以进一步修改掺杂剂分布以使n结成形，使得热载流子从栅极注入。