公开(公告)号：US5858864A

公开(公告)日：1999-01-12

申请号：US939350

申请日：1997-09-29

申请人： Sheldon Aronowitz ,  James Kimball

发明人： Sheldon Aronowitz ,  James Kimball

IPC分类号： H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513

摘要： Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

摘要翻译： 描述了以与衬底中的掺杂区域预定间隔的单晶IV IV半导体衬底中的阻挡区域的形成，以防止或抑制掺杂剂材料通过阻挡区域从相邻掺杂区域的迁移。 通过将IV族材料注入到半导体衬底中至超过掺杂区域的深度的预定深度，可以在半导体中产生阻挡区域，以防止掺杂剂从掺杂区域迁移穿过阻挡区域。 用IV族材料处理单晶衬底以足以在半导体衬底中提供这种势垒区域的剂量和能级进行，但不足以导致半导体单晶晶格的非晶化（破坏） 基质。

公开(公告)号：US5717238A

公开(公告)日：1998-02-10

申请号：US677078

申请日：1996-07-09

申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26506

摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

公开(公告)号：US6033998A

公开(公告)日：2000-03-07

申请号：US38684

申请日：1998-03-09

申请人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

发明人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

IPC分类号： H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823462

摘要： Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

摘要翻译： 提供一种制造在半导体晶片的不同区域上具有可变厚度和组成的栅极电介质层的方法。 在本发明的优选实施例中，首先在各个区域上生长栅氧化层。 具有相对较厚，未硬化的栅极电介质的区域被掩蔽，并且晶片暴露于远程低能量氮等离子体。 在氮化处理完成之后，去除掩模并使晶片进一步氧化。 已经形成氮氧化物的区域用作氧化过程的屏障。 因此，可以在相同的晶片上生长不同的氧化物厚度，在已经进行氮化的情况下更薄并且硬化，并且在氮化期间被掩蔽的那些区域中较厚而不硬化。 根据本发明的可变厚栅极电介质在涉及数字和模拟装置的半导体集成电路中可能是特别有利的。

公开(公告)号：US5904551A

公开(公告)日：1999-05-18

申请号：US631360

申请日：1996-04-12

申请人： Sheldon Aronowitz ,  James Kimball

发明人： Sheldon Aronowitz ,  James Kimball

IPC分类号： H01L21/265 ,  H01L21/70

CPC分类号： H01L21/26513 ,  H01L21/26586

摘要： A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

摘要翻译： 公开了一种用于通过以低能量注入（包括使半导体衬底的晶格定向）来在单晶半导体衬底的表面下方形成一个或多个掺杂区域（例如逆行阱或较深源极/漏极区域）的方法， 到注入光束的轴线，即注入光束中的激发原子的路径，以使在晶格中的原子之间通过的注入原子的数量最大化。 这导致单晶半导体衬底的晶格中的注入原子的峰值浓度比衬底中注入原子的峰值浓度更深，如果注入光束的轴不相对于晶格取向 的半导体衬底。

公开(公告)号：US5707888A

公开(公告)日：1998-01-13

申请号：US434674

申请日：1995-05-04

申请人： Sheldon Aronowitz ,  James Kimball

发明人： Sheldon Aronowitz ,  James Kimball

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S438/911

摘要： A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer. The initial oxide formed by the process appears to be temperature independent, at temperatures of 900.degree. C. or less, with oxide formation apparently dependent upon the extent of the implanted regions of the substrate, rather than upon temperature, resulting in thermal savings. Furthermore, the excess implanted noble gas in the substrate adjacent the oxide formed therein can have beneficial effects in inhibiting the formation of parasitic field transistors and in greater control over field thresholds.

公开(公告)号：US5963801A

公开(公告)日：1999-10-05

申请号：US770109

申请日：1996-12-19

申请人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

发明人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L21/823892

摘要： A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.

摘要翻译： 通过使用低能离子注入机形成CMOS器件中的逆行阱。 将掺杂原子沿着与衬底的表面（具有<100>取向的衬底）正交的方向注入器件衬底的裸露表面。 可以在低于220keV的能量下进行井注入。 逆行井中的穿通屏障的链接植入物可以在植入物之后进行。 当衬底退火时，穿通屏障在逆行井的同时被激活。

公开(公告)号：US07084408B1

公开(公告)日：2006-08-01

申请号：US10697507

申请日：2003-10-29

申请人： James Kimball ,  Sheldon Aronowitz

发明人： James Kimball ,  Sheldon Aronowitz

IPC分类号： H01J27/00 ,  H01J37/08 ,  G21K5/10

CPC分类号： H01J27/04 ,  C23C14/228 ,  C23C14/32 ,  C23C14/48

摘要： Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

摘要翻译： 用加热的惰性载气汽化和处理蒸发的金属元素或金属元素盐进行进一步处理的技术。 蒸发的金属元素或盐由加热至与蒸发温度相同的温度的惰性载气携带到加热的处理室。 金属或盐蒸气可以离子化（和注入）或沉积在基底上。 还提供了用于实现这些技术的装置，其包括载气加热室和加热处理室。

公开(公告)号：US06180470B2

公开(公告)日：2001-01-30

申请号：US08770046

申请日：1996-12-19

申请人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

发明人： Sheldon Aronowitz ,  Laique Khan ,  James Kimball

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S438/925

摘要： Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

摘要翻译： 通过修改器件的LDD区域边界处的电活性LDD掺杂剂的分布来增加短沟道NMOS器件的寿命。 通过在LDD区域的边界处注入反掺杂剂来修改LDD掺杂剂分布。 III族反掺杂剂如硼和IV族元素如硅改变LDD掺杂剂的活化性质。 掺杂剂分布在器件的n结处修改，以减少由器件的栅极和衬底限定的界面处的最大电场位移。 可以进一步修改掺杂剂分布以使n结成形，使得热载流子从栅极注入。

公开(公告)号：US6087229A

公开(公告)日：2000-07-11

申请号：US37588

申请日：1998-03-09

申请人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

发明人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.

摘要翻译： 提供制造硬化复合薄层栅极电介质的方法。 根据本发明的优选实施方案，复合栅极电介质可以制备成具有氮含量高于10原子百分比的氮氧化物部分的双层，同时避免了现有技术氮化方法的缺点。 在本发明的一个方面，可以通过在硅衬底上的非常薄的氧化物层上沉积非常薄的硅层，随后进行低能量等离子体氮化和随后的薄硅氧化来形成硬化的复合薄层栅极电介质 层。 在本发明的另一方面，形成在硅衬底上的薄氧化物层的低能量等离子体氮化可以随后沉积非常薄的硅层，然后沉积薄硅层，随后进行氧化或另外的低能量等离子体氮化，然后氧化 层。

公开(公告)号：US5585286A

公开(公告)日：1996-12-17

申请号：US521795

申请日：1995-08-31

申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

IPC分类号： H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26506

摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入硼的后续剂量 掺杂剂，但不超过与硅衬底中注入约3×1013氩离子/ cm 2相当的量，由此抑制随后注入的硼掺杂剂的通道化和扩散，而不会使半导体衬底非晶化。