NEW SUB 40 NM RESOLUTION Si CONTAINING RESIST SYSTEM
    1.
    发明申请
    NEW SUB 40 NM RESOLUTION Si CONTAINING RESIST SYSTEM 审中-公开
    新SUB 40 NM解决方案Si包含电阻系统

    公开(公告)号:US20070269736A1

    公开(公告)日:2007-11-22

    申请号:US11383548

    申请日:2006-05-16

    IPC分类号: G03C1/00

    摘要: The present invention discloses a resist composition and a method of forming a material structure having a pattern containing features having a dimension of about 40 nm or less by using the inventive resist. The inventive resist comprises a polymer and a photoacid generator. The polymer of the present invention comprises pendant polar moieties, pendant fluoroalcohol moieties, and a backbone containing SiO moieties. In the present invention, at least a portion of the polar moieties are protected with acid labile moieties having a low activation energy. It is preferred that some, but not all, of the pendant fluoroalcohol moieties are protected with acid labile moieties having a low activation energy.

    摘要翻译: 本发明公开了一种抗蚀剂组合物和通过使用本发明的抗蚀剂形成具有尺寸为约40nm或更小的特征的图案的材料结构的方法。 本发明的抗蚀剂包含聚合物和光致酸产生剂。 本发明的聚合物包括极性极性部分,侧基氟代醇部分和含有SiO部分的主链。 在本发明中,至少一部分极性部分被具有低活化能的酸不稳定部分保护。 优选一些而不是全部的侧链氟代醇部分被具有低活化能的酸不稳定部分保护。

    NEGATIVE TONE SILICON-CONTAINING RESIST FOR E-BEAM LITHOGRAPHY
    3.
    发明申请
    NEGATIVE TONE SILICON-CONTAINING RESIST FOR E-BEAM LITHOGRAPHY 失效
    用于电子束光刻的负面含硅含氟电阻

    公开(公告)号:US20080102400A1

    公开(公告)日:2008-05-01

    申请号:US11552677

    申请日:2006-10-25

    IPC分类号: G03C1/00

    摘要: The negative resist compositions especially suitable for electron beam-based lithographic processes are obtained by using a polymeric component containing first silsesquioxane moieties functionalized with a first reactive group having a first crosslinking reactivity and a first dissolution rate in aqueous alkaline solutions, and second silsesquioxane moieties functionalized with a second reactive group having a second crosslinking reactivity and a second dissolution rate in aqueous alkaline solutions, said reactivities being different from one another and said dissolution rates being different from one another. These negative resists enable improved negative lithographic processes, especially in the context of mask-making and direct-write techniques using electron beam lithography. The negative resists are also useful more generally in methods of forming patterned material features and advantageously show reduced incidence of image collapse at smaller groundrules.

    摘要翻译: 特别适用于基于电子束的平版印刷方法的负型抗蚀剂组合物通过使用含有第一倍半硅氧烷部分的聚合物组分获得,所述第一倍半硅氧烷部分用第一反应性基团官能化,所述第一反应性基团具有第一交联反应性和在碱性水溶液中的第一溶解速率,第二倍半硅氧烷部分官能化 具有第二反应性基团,在碱性水溶液中具有第二交联反应性和第二溶解速率,所述反应性彼此不同,并且所述溶解速率彼此不同。 这些负性抗蚀剂能够改善负光刻工艺,特别是在使用电子束光刻的掩模制作和直接写入技术的上下文中。 负型抗蚀剂在更形成图案化材料特征的方法中也更有用,并且有利地显示在较小的基底层上图像塌陷的发生率降低。

    Method for using negative tone silicon-containing resist for e-beam lithography
    4.
    发明授权
    Method for using negative tone silicon-containing resist for e-beam lithography 失效
    用于电子束光刻的负性含硅抗蚀剂的方法

    公开(公告)号:US07399573B2

    公开(公告)日:2008-07-15

    申请号:US11552677

    申请日:2006-10-25

    IPC分类号: G03C7/075

    摘要: The negative resist compositions especially suitable for electron beam-based lithographic processes are obtained by using a polymeric component containing first silsesquioxane moieties functionalized with a first reactive group having a first crosslinking reactivity and a first dissolution rate in aqueous alkaline solutions, and second silsesquioxane moieties functionalized with a second reactive group having a second crosslinking reactivity and a second dissolution rate in aqueous alkaline solutions, said reactivities being different from one another and said dissolution rates being different from one another. These negative resists enable improved negative lithographic processes, especially in the context of mask-making and direct-write techniques using electron beam lithography. The negative resists are also useful more generally in methods of forming patterned material features and advantageously show reduced incidence of image collapse at smaller groundrules.

    摘要翻译: 特别适用于基于电子束的平版印刷方法的负型抗蚀剂组合物通过使用含有第一倍半硅氧烷部分的聚合物组分获得,所述第一倍半硅氧烷部分用第一反应性基团官能化,所述第一反应性基团具有第一交联反应性和在碱性水溶液中的第一溶解速率,第二倍半硅氧烷部分官能化 具有第二反应性基团,在碱性水溶液中具有第二交联反应性和第二溶解速率,所述反应性彼此不同,并且所述溶解速率彼此不同。 这些负性抗蚀剂能够改善负光刻工艺,特别是在使用电子束光刻的掩模制作和直接写入技术的上下文中。 负型抗蚀剂在更形成图案化材料特征的方法中也更有用,并且有利地显示在较小的基底层上图像塌陷的发生率降低。

    Sensor for biomolecules
    5.
    发明授权
    Sensor for biomolecules 有权
    生物分子传感器

    公开(公告)号:US08940548B2

    公开(公告)日:2015-01-27

    申请号:US13552727

    申请日:2012-07-19

    摘要: A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.

    摘要翻译: 用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质,其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。

    Vapor phase deposition processes for doping silicon
    6.
    发明授权
    Vapor phase deposition processes for doping silicon 失效
    掺杂硅的气相沉积工艺

    公开(公告)号:US08691675B2

    公开(公告)日:2014-04-08

    申请号:US12625835

    申请日:2009-11-25

    IPC分类号: H01L21/04

    CPC分类号: H01L21/2254

    摘要: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

    摘要翻译: 用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。 可以以类似的方式形成另外的单层,由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。

    Patterned doping of semiconductor substrates using photosensitive monolayers

    公开(公告)号:US08513642B2

    公开(公告)日:2013-08-20

    申请号:US13541857

    申请日:2012-07-05

    IPC分类号: H01L29/06

    摘要: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

    Multiple orientation nanowires with gate stack stressors
    8.
    发明授权
    Multiple orientation nanowires with gate stack stressors 失效
    具有栅堆叠应力的多取向纳米线

    公开(公告)号:US08368125B2

    公开(公告)日:2013-02-05

    申请号:US12505580

    申请日:2009-07-20

    IPC分类号: H01L27/085

    摘要: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

    摘要翻译: 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外,膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料,使得沿着通道长度的电荷载流子(电子或空穴)的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例,以及制造这种晶体管或芯片的方法。

    Semiconductor nanowire with built-in stress

    公开(公告)号:US07989233B2

    公开(公告)日:2011-08-02

    申请号:US13004340

    申请日:2011-01-11

    IPC分类号: H01L29/06

    摘要: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

    VAPOR PHASE DEPOSITION PROCESSES FOR DOPING SILICON
    10.
    发明申请
    VAPOR PHASE DEPOSITION PROCESSES FOR DOPING SILICON 失效
    用于掺硅的蒸气相沉积工艺

    公开(公告)号:US20110124187A1

    公开(公告)日:2011-05-26

    申请号:US12625835

    申请日:2009-11-25

    IPC分类号: H01L21/22

    CPC分类号: H01L21/2254

    摘要: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

    摘要翻译: 用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。 可以以类似的方式形成另外的单层,由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。