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公开(公告)号：US07631199B2
公开(公告)日：2009-12-08
申请号：US11173784
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
摘要翻译： 描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。 芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态 插件事件。
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公开(公告)号：US07430673B2
公开(公告)日：2008-09-30
申请号：US11173220
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
发明人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , Y02D10/126 , Y02D50/20
摘要： A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.
摘要翻译： 描述了一种用于计算平台的电源管理系统。 在一个实施例中，电源管理系统提供当设备控制器可操作但空闲时，平台的设备控制器假设的附加设备状态。 这些附加设备状态是设备控制器执行某些类型的不活动状态。 在另一个实施例中，电源管理系统提供额外的平台模式，其在模式有效时保证处理器不活动和/或尊重特定平台事件。
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公开(公告)号：US20100083013A1
公开(公告)日：2010-04-01
申请号：US12632548
申请日：2009-12-07
申请人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
摘要翻译： 描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。 芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态 插件事件。
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公开(公告)号：US09052893B2
公开(公告)日：2015-06-09
申请号：US12632548
申请日：2009-12-07
申请人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
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公开(公告)号：US20070005997A1
公开(公告)日：2007-01-04
申请号：US11173784
申请日：2005-06-30
申请人： James Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
摘要翻译： 描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。 芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态 插件事件。
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公开(公告)号：US20070005995A1
公开(公告)日：2007-01-04
申请号：US11173220
申请日：2005-06-30
申请人： James Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
发明人： James Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , Y02D10/126 , Y02D50/20
摘要： A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.
摘要翻译： 描述了一种用于计算平台的电源管理系统。 在一个实施例中，电源管理系统提供当设备控制器可操作但空闲时，平台的设备控制器假设的附加设备状态。 这些附加设备状态是设备控制器执行某些类型的不活动状态。 在另一个实施例中，电源管理系统提供额外的平台模式，其在模式有效时保证处理器不活动和/或尊重特定平台事件。
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公开(公告)号：US07598959B2
公开(公告)日：2009-10-06
申请号：US11169509
申请日：2005-06-29
CPC分类号： G09G5/006 , G09G3/3648 , G09G5/363 , G09G2330/021 , G09G2340/0435
摘要： Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.
摘要翻译： 设备和系统以及方法和物品可以操作来更新视频显示像素。 视频显示总线可以根据指定的时钟频率和刷新时间周期将数据传送到视频显示器。 可以通过调整指定的时钟频率和/或刷新时间来提高功率节省，从而在视频显示总线上提供空闲时间。
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8.发明申请Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications 有权使用中断描述符缓存和异步通知来停止USB活动的方法和设备公开(公告)号：US20070005859A1
公开(公告)日：2007-01-04
申请号：US11171833
申请日：2005-06-29
申请人： Paul Diefenbaugh , James Kardach , Barnes Cooper , Leslie Cline
发明人： Paul Diefenbaugh , James Kardach , Barnes Cooper , Leslie Cline
IPC分类号： G06F13/24
摘要： In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.
摘要翻译： 在一个实施例中，数据处理系统包括但不限于处理器，耦合到处理器的存储器以及耦合到处理器和存储器的通用串行总线（USB）控制器。 USB控制器包括本地存储器，以缓存具有存储在主存储器中的多个帧的周期性调度的至少一部分的至少一个活动描述符。 USB控制器延迟服务于其中一个活动描述符描述的活动USB设备，直到相应的帧被安排在随后的服务中。 还描述了其它方法和装置。
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公开(公告)号：US20150169036A1
公开(公告)日：2015-06-18
申请号：US14109388
申请日：2013-12-17
申请人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
发明人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
CPC分类号： G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为 重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。 描述和要求保护其他实施例。
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公开(公告)号：US08631257B2
公开(公告)日：2014-01-14
申请号：US13445809
申请日：2012-04-12
IPC分类号： G06F1/16
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译： 用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略 。 描述其他实施例。
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