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公开(公告)号：US6145104A
公开(公告)日：2000-11-07
申请号：US22396
申请日：1998-02-12
IPC分类号： G01R31/28 , G06F11/273
CPC分类号： G06F11/2733
摘要： An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel testing of other complex functions in a MCU. The MCU has a plurality of test modes that can be selected, with different peripheral pins being connected to a test circuit depending on which test mode is selected. This allows testing of peripherals via their corresponding pins, as well as other complex functions without the necessity of having dedicated test pins.
摘要翻译： 包含具有多个外部外设引脚的数据处理系统的集成电路利用外围引脚来测试相应的外设以及用于MCU中其他复杂功能的并行测试。 MCU可以选择多种测试模式，根据选择哪种测试模式，不同的外设引脚连接到测试电路。 这允许通过其相应引脚以及其他复杂功能测试外设，而无需专用测试引脚。
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公开(公告)号：US09197231B1
公开(公告)日：2015-11-24
申请号：US14266193
申请日：2014-04-30
CPC分类号： H03M1/468 , H03M1/0639 , H03M1/0675 , H03M1/069 , H03M1/12 , H03M1/38 , H03M1/40 , H03M1/403 , H03M1/46
摘要： Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.
摘要翻译： 公开了将模拟信号电转换为数字信号的系统和方法。 对于第一位值，系统和方法可以包括设置第一转换值以包括第一偏移量; 使用第一比较的输出，设置第二转换值; 并且如果所述第一比特值与所述第一偏移比特值具有预定关系，则从所述第二转换值中移除所述第一偏移量，并且使用所述第二比较的输出来设置第三转换值。
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3.发明授权公开(公告)号：US08477052B2
公开(公告)日：2013-07-02
申请号：US13079818
申请日：2011-04-05
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
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4.发明申请METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权自适应寄存器（SAR）A / D转换器自检的方法和装置公开(公告)号：US20120256774A1
公开(公告)日：2012-10-11
申请号：US13079818
申请日：2011-04-05
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译： 单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。
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公开(公告)号：US20100079325A1
公开(公告)日：2010-04-01
申请号：US12242077
申请日：2008-09-30
IPC分类号： G01B11/00
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.
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6.发明授权Method and apparatus for preventing a data processing system from entering a non-recoverable state 失效防止数据处理系统进入不可恢复状态的方法和装置
公开(公告)号：US5546588A
公开(公告)日：1996-08-13
申请号：US350396
申请日：1994-12-05
CPC分类号： G06F9/30083
摘要： A method and apparatus for preventing a data processing system (10) from entering a non-recoverable state. In one form, the present invention uses a pin (40) to indicate whether or not the execution of a non-recoverable instruction is legal. If the pin indicates that the execution of the instruction is legal, then the instruction is executed and the data processing system (10) is placed into a state that requires an external stimulus in order to recover. If the pin indicates that the execution of the instruction is illegal, then the instruction is not permitted to place the data processing system (10) into a state that requires an external stimulus in order to recover. Instead, an internal recovery mechanism is provided which returns the data processing system (10) to normal processing.
摘要翻译： 一种用于防止数据处理系统（10）进入不可恢复状态的方法和装置。 在一种形式中，本发明使用销（40）来指示不可恢复指令的执行是否合法。 如果引脚指示指令的执行是合法的，则执行指令，并且数据处理系统（10）被置于需要外部刺激以恢复的状态。 如果引脚指示执行指令是非法的，则不允许指令将数据处理系统（10）置于需要外部刺激的状态以便恢复。 而是提供一种将数据处理系统（10）返回到正常处理的内部恢复机制。
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7.发明申请METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权自适应寄存器（SAR）A / D转换器自检的方法和装置公开(公告)号：US20130249723A1
公开(公告)日：2013-09-26
申请号：US13901590
申请日：2013-05-24
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译： 单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。
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公开(公告)号：US20100320997A1
公开(公告)日：2010-12-23
申请号：US12487798
申请日：2009-06-19
IPC分类号： G01R19/00
CPC分类号： G01R31/3008
摘要： A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.
摘要翻译： 提供了一种用于测量被测电路的静态电流的测量电路和方法。 测量电路包括：比较器，具有用于接收参考电压的第一输入端子，耦合到被测电路的第二输入端子和输出端子; 具有耦合到第一电源电压端子的第一端子的电流源和用于向被测电路提供电流的第二端子; 第一开关，其具有耦合到电流源的第二端子的第一端子，耦合到被测电路的第二端子和耦合到比较器的输出端子的控制端子; 以及第一计数器，具有耦合到比较器的输出端的第一输入端，用于接收时钟信号的第二输入端，以及用于提供与静态电流相关联的第一计数值的输出端。
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公开(公告)号：US20100079319A1
公开(公告)日：2010-04-01
申请号：US12242124
申请日：2008-09-30
IPC分类号： H03M1/10
CPC分类号： H03M1/1038 , H03M1/468 , H03M1/68 , H03M1/804
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.
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10.发明授权公开(公告)号：US06661264B2
公开(公告)日：2003-12-09
申请号：US09967180
申请日：2001-09-28
IPC分类号： H03K1722
CPC分类号： H03K17/223
摘要： An integrated circuit may be initialized by determining that the supply voltage is ramping up and resetting logic in the integrated circuit to a predetermined initial state using a reset signal. After the logic is determined to be in its initial state and the supply voltage is established, the reset signal may be latched off.
摘要翻译： 可以通过使用复位信号确定电源电压正在上升并将集成电路中的逻辑复位到预定的初始状态来初始化集成电路。 在确定逻辑处于其初始状态并且建立电源电压之后，可以锁存复位信号。
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